According to an embodiment, a multiphase regulator includes a plurality of output phases each of which is operable to deliver a phase current through a separate inductor to a load connected to the output phases via the inductors and an output capacitor. A controller is operable to regulate a voltage delivered to the load by adjusting the phase currents delivered to the load by the output phases, monitor the phase currents delivered to the load by the output phases, test the output phases in a predetermined sequence, and determine if the phase currents respond in a predetermined way.

The present disclosure relates to an inverter system capable of detecting an output ground fault and an output ground fault detection method using same and, particularly, to an inverter for detecting an output ground fault by detecting the current of a leg-shunt resistor, and an inverter output ground detection fault method using same. The present disclosure compares absolute peak values of 3-phase current AD raw values detected from a shunt resistor, and thus may reliably detect the output ground fault of an inverter.

A signal envelope detector is provided. The signal envelope detector includes an input node configured to receive an input signal. Further, the signal envelope detector includes a capacitive voltage divider coupled to the input node and configured to generate an attenuated input signal by voltage division of the input signal. The signal envelope detector additionally includes a source follower transistor coupled between a first node configured to receive a first voltage supply signal and a second node configured to receive a second voltage supply signal. A gate terminal of the source follower transistor is coupled to the capacitive voltage divider and configured to receive the attenuated input signal. The signal envelope detector includes a rectifier circuit configured to receive and rectify an output signal of the source follower transistor. In addition, the signal envelope detector includes a low-pass filter coupled to the rectifier circuit and configured to generate an envelope signal indicative of a rectified envelope of the input signal by low-pass filtering of an output signal of the rectifier circuit.

The present disclosure provides an analysis device based on power consumption information about a treadmill. The analysis device includes: a current sensor configured to sense, in real time, a change in instantaneous current generated in the treadmill due to a variation in a load of an electric motor in a case in which a belt of the treadmill is driven while repeating rotational motion at a predetermined speed and an object to be measured exercises while stepping the belt according to the predetermined speed; and a processor configured to determine a movement pattern of the object to be measured based on a value of the change in instantaneous current sensed by the current sensor. Thus, it is possible to monitor a health status of the object to be measured.

A circuit includes a peak detector, a diode, a dynamic clamp circuit, and an offset correction circuit. The peak detector generates a voltage on the peak detector output proportional to a lowest voltage on the peak defector input. The anode of the diode is coupled to the peak detector input. The dynamic clamp circuit is coupled to the peak detector input and is configured to clamp a voltage on the peak detector input responsive to a voltage on the diode's anode being greater than the lowest voltage on the peak detector's input. The offset correction circuit is coupled to the peak detector output and is configured to generate an output signal whose amplitude is offset from an amplitude of the peak detector output.

A circuit includes a peak detector, a diode, a dynamic clamp circuit, and an offset correction circuit. The peak detector generates a voltage on the peak detector output proportional to a lowest voltage on the peak defector input. The anode of the diode is coupled to the peak detector input. The dynamic clamp circuit is coupled to the peak detector input and is configured to clamp a voltage on the peak detector input responsive to a voltage on the diode's anode being greater than the lowest voltage on the peak detector's input. The offset correction circuit is coupled to the peak detector output and is configured to generate an output signal whose amplitude is offset from an amplitude of the peak detector output.

Systems and methods for wideband RF interference detection and suppression include an open-circuit stub, a first voltage peak detector, a second voltage peak detector, an analog-to-digital converter (ADC), and a controller. The open-circuit stub is configured to receive an input signal. The first voltage peak detector is coupled at the open end of the open-circuit stub and configured to output a first voltage signal based on a portion of the input signal. The second voltage peak detector is coupled a distance away from the open end of the open-circuit stub and configured to output a second voltage signal based on the portion of the input signal. The controller is configured to generate an output control signal operable to adjust a signal filter based on the first digital voltage signal and the second digital voltage signal to suppress the portion of the input signal.

Systems and methods for wideband RF interference detection and suppression include an open-circuit stub, a first voltage peak detector, a second voltage peak detector, an analog-to-digital converter (ADC), and a controller. The open-circuit stub is configured to receive an input signal. The first voltage peak detector is coupled at the open end of the open-circuit stub and configured to output a first voltage signal based on a portion of the input signal. The second voltage peak detector is coupled a distance away from the open end of the open-circuit stub and configured to output a second voltage signal based on the portion of the input signal. The controller is configured to generate an output control signal operable to adjust a signal filter based on the first digital voltage signal and the second digital voltage signal to suppress the portion of the input signal.

A signal detector circuit includes a signal peak detector circuit, a reference voltage generation circuit, and a comparator circuit. The signal peak detector circuit is arranged to receive a plurality of differential voltage input signals, and generate a single-ended peak signal according to the plurality of differential voltage input signals. The reference voltage generation circuit is arranged to generate a single-ended reference voltage signal. The comparator circuit is arranged to receive the single-ended peak signal and the single-ended reference voltage signal, and compare the single-ended peak signal with the single-ended reference voltage signal to generate a signal detection result.

A signal detector circuit includes a signal peak detector circuit, a reference voltage generation circuit, and a comparator circuit. The signal peak detector circuit is arranged to receive a plurality of differential voltage input signals, and generate a single-ended peak signal according to the plurality of differential voltage input signals. The reference voltage generation circuit is arranged to generate a single-ended reference voltage signal. The comparator circuit is arranged to receive the single-ended peak signal and the single-ended reference voltage signal, and compare the single-ended peak signal with the single-ended reference voltage signal to generate a signal detection result.