An electric motor controller and methods of determining which input power line of a plurality of input power lines of a motor drive controller has been energized are provided. An electric motor controller configured to be coupled to an electric motor includes a plurality of power input lines configured to receive an alternating current (AC) input voltage from an AC power source, an energized line detection device configured to sense that a power input line has been energized by the AC power source, and configured to output an isolated signal, and a rectifier configured to convert the AC input voltage having a frequency to a direct current (DC) voltage. The controller also includes a computing device coupled downstream from the energized line detection device and configured to determine which input power line has been energized.

An electric motor controller and methods of determining which input power line of a plurality of input power lines of a motor drive controller has been energized are provided. An electric motor controller configured to be coupled to an electric motor includes a plurality of power input lines configured to receive an alternating current (AC) input voltage from an AC power source, an energized line detection device configured to sense that a power input line has been energized by the AC power source, and configured to output an isolated signal, and a rectifier configured to convert the AC input voltage having a frequency to a direct current (DC) voltage. The controller also includes a computing device coupled downstream from the energized line detection device and configured to determine which input power line has been energized.

A computer including a hardware interface wherein the hardware interface includes a first resistor with a first first resistor pin and a second first resistor pin, a second resistor with a first second resistor pin and a second second resistor pin, a transistor, a comparator; the first first resistor pin being coupled on the one hand to the first hardware interface pin and on the other hand to a first transistor pin.

Disclosed is a power failure detection circuit, including a first PMOS FET (mp1), a second PMOS FET (mp2), a first NMOS FET (mn2), a second NMOS FET (mn3) and a reset transistor (mn1). The PN junction area of the drain electrode of the first PMOS FET (mp1) is greater than the PN junction area of the drain electrode of the first NMOS FET (mn2). The PN junction area of the drain electrode of the second NMOS FET (mn3) is greater than the PN junction area of the drain electrode of the second PMOS FET (mp2). The power failure detection circuit of the present invention is novel in design and high in practicability.

Disclosed is a power failure detection circuit, including a first PMOS FET (mp1), a second PMOS FET (mp2), a first NMOS FET (mn2), a second NMOS FET (mn3) and a reset transistor (mn1). The PN junction area of the drain electrode of the first PMOS FET (mp1) is greater than the PN junction area of the drain electrode of the first NMOS FET (mn2). The PN junction area of the drain electrode of the second NMOS FET (mn3) is greater than the PN junction area of the drain electrode of the second PMOS FET (mp2). The power failure detection circuit of the present invention is novel in design and high in practicability.

The invention relates to a circuit arrangement for combined protection of a load from temporary and transient overvoltages with emergency operation of the load in the presence of a temporary overvoltage and with integrated follow current limitation, wherein a first surge arrester, in particular a spark gap or a varistor, is provided between network-side input terminals and a second surge arrester, in particular a varistor, is provided between load-side output terminals for follow current limitation. According to the invention, at least one controlled semiconductor switch is provided in each case in the series branch between the input terminal and the output terminal and in the output-side parallel branch, wherein a mechanical switch and a series capacitance are connected in parallel with the semiconductor switch in the series branch. Furthermore, the semiconductor switch in the parallel branch is part of a series circuit comprising a parallel circuit comprising a second surge arrester and a parallel capacitance. A series inductance is provided in the series branch between the input terminal and the parallel circuit comprising the series capacitance, the controlled semiconductor switch and the mechanical switch. A microcontroller for controlling the semiconductor switches is also present, wherein the microcontroller is connected to a current detector in the series branch.

The invention relates to a circuit arrangement for combined protection of a load from temporary and transient overvoltages with emergency operation of the load in the presence of a temporary overvoltage and with integrated follow current limitation, wherein a first surge arrester, in particular a spark gap or a varistor, is provided between network-side input terminals and a second surge arrester, in particular a varistor, is provided between load-side output terminals for follow current limitation. According to the invention, at least one controlled semiconductor switch is provided in each case in the series branch between the input terminal and the output terminal and in the output-side parallel branch, wherein a mechanical switch and a series capacitance are connected in parallel with the semiconductor switch in the series branch. Furthermore, the semiconductor switch in the parallel branch is part of a series circuit comprising a parallel circuit comprising a second surge arrester and a parallel capacitance. A series inductance is provided in the series branch between the input terminal and the parallel circuit comprising the series capacitance, the controlled semiconductor switch and the mechanical switch. A microcontroller for controlling the semiconductor switches is also present, wherein the microcontroller is connected to a current detector in the series branch.

A flexible sheet-type leak sensor device according to the present invention comprises: a flexible base sheet made of a non-conductive fluorine-based synthetic resin comprising ethylene tetrafluoroethylene (ETFE); conductive lines formed on a surface of the base sheet so as to have a predetermined pattern and so as not to meet or cross each other, the conductive lines being formed by depositing on the base sheet surface a carbon black-containing, conductive fluorine-based synthetic resin comprising ethylene tetrafluoroethylene (ETFE); and a conductive material composed of pure carbon black, formed at the bottom of the conductive lines.

According to one embodiment, an electronic apparatus connectable to an external apparatus includes a first connector and a detector. The first connecter is electrically connected to a second connector of the external apparatus. Each of the first connector and the second connecter includes a plurality of terminals. The detector is configured to detect a state of a first terminal of the first connector. The first terminal of the first connector is configured to be set to a predetermined state via at least a connection line connecting two terminals of the second connector to each other while the first connector and the second connector are electrically connected to each other.

According to one embodiment, an electronic apparatus connectable to an external apparatus includes a first connector and a detector. The first connecter is electrically connected to a second connector of the external apparatus. Each of the first connector and the second connecter includes a plurality of terminals. The detector is configured to detect a state of a first terminal of the first connector. The first terminal of the first connector is configured to be set to a predetermined state via at least a connection line connecting two terminals of the second connector to each other while the first connector and the second connector are electrically connected to each other.