System and method for charging or discharging one or more batteries. For example, a battery management system for charging or discharging one or more batteries includes: a first transistor including a first transistor terminal, a second transistor terminal, and a third transistor terminal, the second transistor terminal being configured to receive a first drive signal; a second transistor including a fourth transistor terminal, a fifth transistor terminal, and a sixth transistor terminal, the fifth transistor terminal being configured to receive a second drive signal; a burst mode detector configured to receive the first drive signal and generate a burst-mode detection signal based at least in part on the first drive signal; and a drive signal generator configured to receive the burst-mode detection signal and generate the first drive signal and the second drive signal based at least in part on the burst-mode detection signal.

A converter operable to convert an input voltage at an input node to an output voltage at an output node coupled to a load by switching on and off a transistor at a switching frequency, the converter comprising: an error amplifier circuit having a first input coupled to a reference voltage, a second input coupled to the output node through a resistive divider, a first output operable to output a control current and a second output operable to output a current equivalent to the control current; a peak current comparator circuit having a first input coupled to the second output of the error amplifier circuit, a second input and an output, the second input is coupled to the input node through an inductor; an off-time timer circuit having an input coupled to the first output of the error amplifier circuit and an output, the off-time timer circuit operable to set the switching frequency based on the control current; and a control circuit having a first input coupled to the output of the peak current comparator circuit, a second input coupled to the output of the off-time timer circuit and an output coupled to a control terminal of the transistor.

An apparatus, system and method of controlling the supply of DC current from a power source to an electrical load provides for a protective circuit that senses the characteristics of the connected load prior to permitting the enablement of a switch connecting the supply and the load. A voltage arising from applying a constant current to the load during a time period is compared with a predetermined threshold determined by the intended capacity of the switch so that, when closed, the current through the switch is compatible with the switch. The protective circuit may be used in conjunction with semiconductor switches, electromechanical contactors or relays. A plurality of such devices may be incorporated in an enclosure and controlled by logic so as to manage the supply of power from a power source to a plurality of electrical loads having differing power requirements.

In one example, an arc fault circuit interrupter (AFCI) is provided. The AFCI may include a plurality of current arc signature detection blocks configured to output a plurality of corresponding current arc signatures, and a processor. The processor may be configured to receive each of the plurality of current arc signature from each of plurality of current arc signature detection blocks, respectively, and generate a first trigger signal. The processor may be further configured to assess each of the current arc signatures, determine whether an arc fault exists based on the assessment, and generate the first trigger signal if an arc fault is determined to exist. A method for detecting an arc fault is also provided.

A first terminal receives a first DC voltage. A switch selectively couples the first terminal to a second terminal providing an output. A control circuit selectively actuates the switch in response to a comparison of the first DC voltage to a second DC voltage. A low-dropout (LDO) linear voltage regulator, connected between the first and third terminals, operates to provide the second DC voltage from the first DC voltage.

An open circuit diagnosis apparatus, and method for open circuit diagnosis, for a motor drive circuit with a Miller plateau detection unit that detects whether there is a Miller plateau region in a gate voltage applied to a switching element of a motor drive circuit when the switching element is turned on; a body diode activation detection unit which detects whether the body diode of the switching element has been activated which depends on the on/off state of the switching element; and a control unit which determines whether the motor drive circuit is in the open circuit state on the basis of whether the body diode activation unit has been activated and whether there is a Miller plateau region in a gate voltage.

Disclosed is a power failure detection circuit, including a first PMOS FET (mp1), a second PMOS FET (mp2), a first NMOS FET (mn2), a second NMOS FET (mn3) and a reset transistor (mn1). The PN junction area of the drain electrode of the first PMOS FET (mp1) is greater than the PN junction area of the drain electrode of the first NMOS FET (mn2). The PN junction area of the drain electrode of the second NMOS FET (mn3) is greater than the PN junction area of the drain electrode of the second PMOS FET (mp2). The power failure detection circuit of the present invention is novel in design and high in practicability.

A resonance voltage attenuation detection circuit detects attenuation of a resonance voltage of a winding of a transformer. The resonance voltage attenuation detection circuit includes a first voltage comparator circuit and a time-out circuit. The first voltage comparator circuit compares a voltage of the winding with a predetermined first voltage. The time-out circuit performs clocking operation in accordance with an output of the first voltage comparator circuit. The time-out circuit outputs an attenuation detection signal when the time-out circuit has clocked a preset period which is shorter than a time required for a peak voltage of the winding to be attenuated from the first voltage to a predetermined second voltage lower than the first voltage.

Disclosed is a power failure detection device and method capable of issuing a power failure alert early. The device includes a voltage reduction circuit, a detection voltage generating circuit, a detection circuit, and a transmitting circuit. The voltage reduction circuit is or includes at least one active electronic component, and generates an output voltage according to an input voltage higher than the output voltage. The detection voltage generating circuit is coupled between the voltage reduction circuit and a low voltage terminal, and generates a detection voltage according to the output voltage that is between the output voltage and the voltage of the low voltage terminal. The detection circuit generates a detection result according to the detection voltage and a trigger voltage. The transmitting circuit sends a power failure alert to a far-end device on condition that the detection result indicates that the detection voltage is lower than the trigger voltage.

A fault monitoring device may monitor and detect for faults corresponding to a high-side voltage rail, to low-side voltage rail, or internally within a voltage source connected to the high-side voltage rail and the low-side voltage rail. The fault monitoring device may determine sample voltage levels and/or sample resistance values to detect the faults. Also, in various embodiments, the fault monitoring device may perform one or more fault monitoring processes over multiple stages. The fault monitoring device may determine the sample voltage levels and/or the sample resistance values while switching a secondary resistance circuit in different states over the multiple stages.