Embodiments described herein provide a zero-crossing detector (ZCD) for a direct current to direct current (DC-DC) converter. The ZCD includes a ZCD integrator configured to receive a switch voltage and an output voltage of a power stage of the DC-DC converter and to generate a zero-crossing detect signal based, at least in part, on the received switch voltage and output voltage, where the zero-crossing detect signal is configured to indicate an output current in an output inductor of the power stage of the DC-DC converter is approximately zero. The ZCD may also include a ZCD offset calibrator configured to receive the switch voltage and generate a ZCD calibration offset based, at least in part, on the received switch voltage, where the ZCD integrator is configured to generate the zero-crossing detect signal based, at least in part, on the ZCD calibration offset.

Embodiments described herein provide a zero-crossing detector (ZCD) for a direct current to direct current (DC-DC) converter. The ZCD includes a ZCD integrator configured to receive a switch voltage and an output voltage of a power stage of the DC-DC converter and to generate a zero-crossing detect signal based, at least in part, on the received switch voltage and output voltage, where the zero-crossing detect signal is configured to indicate an output current in an output inductor of the power stage of the DC-DC converter is approximately zero. The ZCD may also include a ZCD offset calibrator configured to receive the switch voltage and generate a ZCD calibration offset based, at least in part, on the received switch voltage, where the ZCD integrator is configured to generate the zero-crossing detect signal based, at least in part, on the ZCD calibration offset.

A method for measuring parameters of an analog signal to determine times at which the analog signal (S) crosses predetermined voltage thresholds (V.sub.A, V.sub.B, V.sub.C, V.sub.D), the method comprising the steps of: splitting the analog signal (S) into a number of interim signals (S.sub.A, S.sub.B, S.sub.C, S.sub.D), the number of the interim signals corresponding to the number of the preset voltage thresholds (V.sub.A, V.sub.B, V.sub.C, V.sub.D); providing an FPGA system (10) comprising differential buffers (11 A, 11 B, 11 C, 11 D) with outputs connected to a number of sequences (20A, 20B, 20C, 20D) of delay elements (21, 22, 23), the number of sequences of delay elements corresponding to the number of the preset voltage thresholds (V.sub.A, V.sub.B, V.sub.C, V.sub.D); inputting, to an input of each differential buffer (11 A, 11 B, 11 C, 11 D), one interim signal (S.sub.A, S.sub.B, S.sub.C, S.sub.D) and a reference voltage corresponding to a particular preset voltage threshold (V.sub.A, V.sub.B, V.sub.C, V.sub.D); reading, by means of vector generators (31 A, 31 B, 31 C, 31 D), assigned separately to each of the sequences (20A, 20B, 20C, 20D) and connected to a common clock signal (CLK), current values of output signals of each of the delay elements (21, 22, 23) in the particular sequence (20A, 20B, 20C, 20D) at the same moment for all vector generators and providing these values as sequence output vectors (W.sub.A, W.sub.B, W.sub.C, W.sub.D); and determining times at which the analog signal (S) crosses the predetermined voltage thresholds (V.sub.A, V.sub.B, V.sub.C, V.sub.D) on the basis of the values of the sequence output vectors (W.sub.A, W.sub.B, W.sub.C, W.sub.D) and the delays introduced by the delay elements (21, 22, 23).

A method for measuring parameters of an analog signal to determine times at which the analog signal (S) crosses predetermined voltage thresholds (V.sub.A, V.sub.B, V.sub.C, V.sub.D), the method comprising the steps of: splitting the analog signal (S) into a number of interim signals (S.sub.A, S.sub.B, S.sub.C, S.sub.D), the number of the interim signals corresponding to the number of the preset voltage thresholds (V.sub.A, V.sub.B, V.sub.C, V.sub.D); providing an FPGA system (10) comprising differential buffers (11 A, 11 B, 11 C, 11 D) with outputs connected to a number of sequences (20A, 20B, 20C, 20D) of delay elements (21, 22, 23), the number of sequences of delay elements corresponding to the number of the preset voltage thresholds (V.sub.A, V.sub.B, V.sub.C, V.sub.D); inputting, to an input of each differential buffer (11 A, 11 B, 11 C, 11 D), one interim signal (S.sub.A, S.sub.B, S.sub.C, S.sub.D) and a reference voltage corresponding to a particular preset voltage threshold (V.sub.A, V.sub.B, V.sub.C, V.sub.D); reading, by means of vector generators (31 A, 31 B, 31 C, 31 D), assigned separately to each of the sequences (20A, 20B, 20C, 20D) and connected to a common clock signal (CLK), current values of output signals of each of the delay elements (21, 22, 23) in the particular sequence (20A, 20B, 20C, 20D) at the same moment for all vector generators and providing these values as sequence output vectors (W.sub.A, W.sub.B, W.sub.C, W.sub.D); and determining times at which the analog signal (S) crosses the predetermined voltage thresholds (V.sub.A, V.sub.B, V.sub.C, V.sub.D) on the basis of the values of the sequence output vectors (W.sub.A, W.sub.B, W.sub.C, W.sub.D) and the delays introduced by the delay elements (21, 22, 23).

A circuit and a method for detecting a current zero-crossing point, and a circuit and method for detecting a load voltage are disclosed. The circuit for detecting current zero-crossing point includes: a load power supply circuit (14), a voltage-dividing resistor (16), a transistor switch (15), a zero-crossing detection circuit (19); the load power supply circuit (14) includes: a load (11), a diode (13), and an inductor (12); one end of the load power supply circuit (14) is connected with the operating voltage input terminal, the other end of the load power supply circuit (14) is connected with a first end of the transistor switch (15) and a first end of the voltage-dividing resistor (16), a second end of the voltage-dividing resistor (16) and a second end of the transistor switch (15) are connected with the ground, the load voltage is controlled by the transistor switch (15), the voltage-dividing terminal of the voltage-dividing resistor (16) is connected to a signal input terminal of the zero-crossing detection circuit (19), the zero-crossing detection circuit (19) is used to determine whether the current of the diode (13) crosses zero to obtain the on time of the diode (13), and the circuit for detecting load voltage uses the on time of the diode (13) and the on time of the transistor switch (15) to obtain the load voltage. The circuits are simple, but with high detection efficiency and low cost.

A circuit and a method for detecting a current zero-crossing point, and a circuit and method for detecting a load voltage are disclosed. The circuit for detecting current zero-crossing point includes: a load power supply circuit (14), a voltage-dividing resistor (16), a transistor switch (15), a zero-crossing detection circuit (19); the load power supply circuit (14) includes: a load (11), a diode (13), and an inductor (12); one end of the load power supply circuit (14) is connected with the operating voltage input terminal, the other end of the load power supply circuit (14) is connected with a first end of the transistor switch (15) and a first end of the voltage-dividing resistor (16), a second end of the voltage-dividing resistor (16) and a second end of the transistor switch (15) are connected with the ground, the load voltage is controlled by the transistor switch (15), the voltage-dividing terminal of the voltage-dividing resistor (16) is connected to a signal input terminal of the zero-crossing detection circuit (19), the zero-crossing detection circuit (19) is used to determine whether the current of the diode (13) crosses zero to obtain the on time of the diode (13), and the circuit for detecting load voltage uses the on time of the diode (13) and the on time of the transistor switch (15) to obtain the load voltage. The circuits are simple, but with high detection efficiency and low cost.

Provided is a zero-crossing detection circuit capable of detecting zero-crossing with high accuracy without being influenced by noise. The zero-crossing detection circuit includes a first comparison circuit, a second comparison circuit having a hysteresis function, and a logic circuit. The first comparison circuit is configured to output a zero-crossing detection result of a first input signal and a second input signal. The second comparison circuit is configured to output a comparison result of the first input signal and the second input signal. The logic circuit includes a unit configured to determine whether to reflect the zero-crossing detection result to output of the logic circuit based on the zero-crossing detection result and the comparison result.

Provided is a zero-crossing detection circuit capable of detecting zero-crossing with high accuracy without being influenced by noise. The zero-crossing detection circuit includes a first comparison circuit, a second comparison circuit having a hysteresis function, and a logic circuit. The first comparison circuit is configured to output a zero-crossing detection result of a first input signal and a second input signal. The second comparison circuit is configured to output a comparison result of the first input signal and the second input signal. The logic circuit includes a unit configured to determine whether to reflect the zero-crossing detection result to output of the logic circuit based on the zero-crossing detection result and the comparison result.

A power converter is provided. A driver circuit is connected between a controller circuit and a switch circuit. The switch circuit is connected to an inductor. The inductor is connected in series with a first capacitor and grounded through the first capacitor. A first comparison input terminal of a first comparator is connected to an output terminal between the inductor and the first capacitor. A second comparison input terminal of the first comparator is grounded through a second capacitor. The controller circuit outputs a control signal for controlling the driver circuit to drive the switch circuit according to a comparison signal outputted by the first comparator. A reference current source provides a reference current to the second capacitor. A first terminal of a first resistor is connected to the second capacitor. A second terminal of the first resistor is coupled to a reference potential.

A power converter is provided. A driver circuit is connected between a controller circuit and a switch circuit. The switch circuit is connected to an inductor. The inductor is connected in series with a first capacitor and grounded through the first capacitor. A first comparison input terminal of a first comparator is connected to an output terminal between the inductor and the first capacitor. A second comparison input terminal of the first comparator is grounded through a second capacitor. The controller circuit outputs a control signal for controlling the driver circuit to drive the switch circuit according to a comparison signal outputted by the first comparator. A reference current source provides a reference current to the second capacitor. A first terminal of a first resistor is connected to the second capacitor. A second terminal of the first resistor is coupled to a reference potential.