In certain aspects, a method is provided for measuring power using a resistive element coupled between a power amplifier and an antenna. The method includes squaring a voltage from a first terminal of the resistive element to obtain a first signal, squaring a voltage from a second terminal of the resistive element to obtain a second signal, and generating a measurement signal based on a difference between the first signal and the second signal. In some implementations, the resistive element is implemented with a power switch.

A power detector measures RF power delivered into a first load of uncertain impedance. A reference power meter measures power of a reference signal to a second load of known impedance. The reference power meter measures voltage across the second load; measures a current through the second load; and multiplies the measured voltage by the measured current to generate a reference power signal proportional to power delivered to the second load. A measurement power meter measures power of a signal to the first load. The measurement power meter measures voltage across the first load; measures current through the first load; and multiplies the measured voltage by the measured current to generate a measured power signal proportional to power delivered to the first load. The power detector includes a processor to calculate power delivered to the second load, and to generate a power delivered to the first load.

A power detector constituted of: a transconductance element arranged to output a rectified detection current, the magnitude thereof arranged to increase exponentially responsive to a linear increase in the amplitude of an input signal; and at least one p-n junction based device, a function of the rectified detection current arranged to flow there through. The output of the power detector is a function of the voltage across the at least one p-n junction based device.

A power detector constituted of: a transconductance element arranged to output a rectified detection current, the magnitude thereof arranged to increase exponentially responsive to a linear increase in the amplitude of an input signal; and at least one p-n junction based device, a function of the rectified detection current arranged to flow there through. The output of the power detector is a function of the voltage across the at least one p-n junction based device.

A system includes a first circuit and a second circuit. The first circuit includes a first MOS transistor having a gate and a drain. The first circuit is configured to receive a radio frequency (RF) signal at the gate of the first MOS transistor. The drain of the first MOS transistor is configured to output a first current that is proportional to the square of the input voltage of the RF signal while receiving the RF signal. The second circuit includes a second MOS transistor having a source configured to receive a first current from the first circuit. The second MOS transistor is biased in a triode region and has a channel resistance between the source and a drain. The second circuit is configured to output a voltage proportional to the value of the power of the RF signal received by the first circuit.

A system includes a first circuit and a second circuit. The first circuit includes a first MOS transistor having a gate and a drain. The first circuit is configured to receive a radio frequency (RF) signal at the gate of the first MOS transistor. The drain of the first MOS transistor is configured to output a first current that is proportional to the square of the input voltage of the RF signal while receiving the RF signal. The second circuit includes a second MOS transistor having a source configured to receive a first current from the first circuit. The second MOS transistor is biased in a triode region and has a channel resistance between the source and a drain. The second circuit is configured to output a voltage proportional to the value of the power of the RF signal received by the first circuit.

A power detector comprising a first and a second bipolar junction/FET transistor. The first transistor is arranged as a common base/gate transistor with its base/gate being biased by a bias voltage and the second transistor is arranged as a common emitter/source transistor with its emitter/source being grounded. The power detector also comprises a diode or current source connected to ground from the emitter/source of the first transistor, in which power detector an input port is connected to the emitter of the first transistor and to the base/gate of the second transistor, and an output port is connected to the collectors/drains of the first and second transistor, said collectors/drains also being connected to a DC supply via a first resistor.

A power detector comprising a first and a second bipolar junction/FET transistor. The first transistor is arranged as a common base/gate transistor with its base/gate being biased by a bias voltage and the second transistor is arranged as a common emitter/source transistor with its emitter/source being grounded. The power detector also comprises a diode or current source connected to ground from the emitter/source of the first transistor, in which power detector an input port is connected to the emitter of the first transistor and to the base/gate of the second transistor, and an output port is connected to the collectors/drains of the first and second transistor, said collectors/drains also being connected to a DC supply via a first resistor.

Methods and systems for a wideband CMOS RMS power detection scheme may comprise: a first circuit including a first metal oxide semiconductor (MOS) transistor having a gate for receiving a radio frequency (RF) signal and having a drain for outputting a first current that is proportional to a square of a voltage of the RF signal in response to receiving the RF signal; and a second circuit connected to the first circuit, the second circuit comprising a second MOS transistor biased in a triode region and having a source for receiving the first current from the first circuit. The second circuit may output a voltage proportional to a power of the RF signal received by the first circuit, the output voltage being a function of the first current and a channel resistance of the second MOS transistor.

Methods and systems for a wideband CMOS RMS power detection scheme may comprise: a first circuit including a first metal oxide semiconductor (MOS) transistor having a gate for receiving a radio frequency (RF) signal and having a drain for outputting a first current that is proportional to a square of a voltage of the RF signal in response to receiving the RF signal; and a second circuit connected to the first circuit, the second circuit comprising a second MOS transistor biased in a triode region and having a source for receiving the first current from the first circuit. The second circuit may output a voltage proportional to a power of the RF signal received by the first circuit, the output voltage being a function of the first current and a channel resistance of the second MOS transistor.