A count processor counts a zero crossing detection count C. A fraction processor for calculating a fraction F.sub.j (j=1 to L) of the zero crossing detection count on the basis of the digital signal at sampling timings immediately before a zero crossing specifying and when the zero crossing specifying, and computing a fraction processing parameter G.sub.j=N.sub.jF.sub.j using a zero crossing detection number N.sub.j(0N.sub.jN1) in a period corresponding to a sampling count N necessary for averaging determined in advance. The averaging is performed according to the following formula, where C is the output of the count processor at the end of an averaging period and G.sub.j (j=1 to L) is L fraction processing parameters (L indicates the number of G.sub.j included between the averaging counts N) computed by the fraction processor, and the phase of the digital signal is computed, whereby the phase is calculated on the basis of an input signal digital value obtained by an AD converter. $\begin{array}{cc}U=C-\frac{1}{N}\underset{j=1}{\overset{L}{.Math.}}{G}_j& \left(\mathrm{Formula}1\right)\end{array}$

A count processor counts a zero crossing detection count C. A fraction processor for calculating a fraction F.sub.j (j=1 to L) of the zero crossing detection count on the basis of the digital signal at sampling timings immediately before a zero crossing specifying and when the zero crossing specifying, and computing a fraction processing parameter G.sub.j=N.sub.jF.sub.j using a zero crossing detection number N.sub.j(0N.sub.jN1) in a period corresponding to a sampling count N necessary for averaging determined in advance. The averaging is performed according to the following formula, where C is the output of the count processor at the end of an averaging period and G.sub.j (j=1 to L) is L fraction processing parameters (L indicates the number of G.sub.j included between the averaging counts N) computed by the fraction processor, and the phase of the digital signal is computed, whereby the phase is calculated on the basis of an input signal digital value obtained by an AD converter. $\begin{array}{cc}U=C-\frac{1}{N}\underset{j=1}{\overset{L}{.Math.}}{G}_j& \left(\mathrm{Formula}1\right)\end{array}$

An electronic circuitry is proposed. The electronic circuitry comprises a directional coupler comprising a first port configured to receive an input signal from a signal source, a second port configured to output the input signal for transmission to a load, a third port configured to output a forward signal based on the input signal, and a fourth port configured to output a reverse signal based on a reflection of the input signal received at the second port. The electronic circuitry further comprises a Time-to-Digital converter, TDC, coupled to the third port and the fourth port. The TDC is configured to determine a phase difference between the forward signal and the reverse signal.

This phase measurement device is provided with: a count processor 4 that counts a zero crossing detection count C, which is the number of times a change in the sign of a digital signal has been detected; and a fraction processor 5 for calculating a fraction F.sub.j (j=1 to L) of the zero crossing detection count on the basis of the digital signal at sampling timings immediately before and immediately after a zero crossing specification means has determined a zero crossing, and computing a fraction processing parameter G.sub.j=N.sub.jF.sub.j using a zero crossing detection number N.sub.j (1N.sub.jN) in a period corresponding to a sampling count N necessary for averaging determined in advance. The averaging is performed according to the following formula, where C is the output of the count processor at the end of an averaging period and G.sub.j (j=1 to L) is L fraction processing parameters computed by the fraction processor, and the phase of the digital signal is computed, whereby the phase is calculated on the basis of an input signal digital value obtained by an AD converter.

[00001]$\begin{array}{cc}U=C-\frac{1}{N}.Math.\underset{j=1}{\overset{L}{.Math.}}.Math..Math.G_j& \left(\mathrm{Formula}.Math..Math.1\right)\end{array}$

This phase measurement device is provided with: a count processor 4 that counts a zero crossing detection count C, which is the number of times a change in the sign of a digital signal has been detected; and a fraction processor 5 for calculating a fraction F.sub.j (j=1 to L) of the zero crossing detection count on the basis of the digital signal at sampling timings immediately before and immediately after a zero crossing specification means has determined a zero crossing, and computing a fraction processing parameter G.sub.j=N.sub.jF.sub.j using a zero crossing detection number N.sub.j (1N.sub.jN) in a period corresponding to a sampling count N necessary for averaging determined in advance. The averaging is performed according to the following formula, where C is the output of the count processor at the end of an averaging period and G.sub.j (j=1 to L) is L fraction processing parameters computed by the fraction processor, and the phase of the digital signal is computed, whereby the phase is calculated on the basis of an input signal digital value obtained by an AD converter.

[00001]$\begin{array}{cc}U=C-\frac{1}{N}.Math.\underset{j=1}{\overset{L}{.Math.}}.Math..Math.G_j& \left(\mathrm{Formula}.Math..Math.1\right)\end{array}$

The present disclosure relates to phase measurement circuitry operable based on a first clock signal having an intended clock frequency F1 and a second clock signal having an intended clock frequency F2, the circuitry comprising: a delay line configured to receive the first clock signal, the delay line comprising a plurality of delay units each configured to cause a propagation delay, and the plurality of delay units connected in series along the length of the delay line and defining a series of positions therebetween through which signal edges of the first clock signal propagate over time; an edge detector configured to sample the delay line at successive sample times based on the second clock signal and to record at each sample time the position of a given signal edge of the first clock signal along the delay line; and a phase angle determiner configured to determine a phase angle per delay unit based on successive recorded said positions.

The present disclosure relates to phase measurement circuitry operable based on a first clock signal having an intended clock frequency F1 and a second clock signal having an intended clock frequency F2, the circuitry comprising: a delay line configured to receive the first clock signal, the delay line comprising a plurality of delay units each configured to cause a propagation delay, and the plurality of delay units connected in series along the length of the delay line and defining a series of positions therebetween through which signal edges of the first clock signal propagate over time; an edge detector configured to sample the delay line at successive sample times based on the second clock signal and to record at each sample time the position of a given signal edge of the first clock signal along the delay line; and a phase angle determiner configured to determine a phase angle per delay unit based on successive recorded said positions.

A method and device for sorting grounded electrical conductors according to phase. Different high-current pulsed sequences are applied to each of the electrical conductors of a first three-phase conductor in an electrical power network. Pulsed current sequences applied to the three electrical conductors of the first conductor, seeking an electrical ground, will be detectable on the electrical conductors of each of the conductors in parallel with the electrical conductors of the first conductor. A detector detects a magnetic-pulsed sequence associated with the current-pulsed sequences on the electrical conductors and matches it to one of the corresponding current-pulsed sequences on the electrical conductors of the first three-phase conductor, thereby decoding the sequence to identify the phases of each of the conductors. Each electrical conductor is then tagged with its phase before the conductor network is ungrounded and energized.

A phase detection circuit includes a sampling signal generation circuit configured to generate a plurality of sampling signals in response to a plurality of phase change clocks having different phases and data; a charging voltage generation circuit configured to compare the plurality of sampling signals, and change a voltage level of one charging voltage between a first charging voltage and a second charging voltage; and a comparison circuit configured to compare voltage levels of the first and second charging voltages, and generate a result signal.

A phase detection circuit includes a sampling signal generation circuit configured to generate a plurality of sampling signals in response to a plurality of phase change clocks having different phases and data; a charging voltage generation circuit configured to compare the plurality of sampling signals, and change a voltage level of one charging voltage between a first charging voltage and a second charging voltage; and a comparison circuit configured to compare voltage levels of the first and second charging voltages, and generate a result signal.