Methods and circuitry are disclosed to produce a first signal representative of the AC voltage signal and a second signal representative of an AC current signal. The first and second signals may be combined with a clock signal to produce a third signal. A phase angle between the AC voltage signal and the AC current signal may be determined based on a pulse count indicative of how many pulses occur in the third signal over a predetermined period of time.

Methods and circuitry are disclosed to produce a first signal representative of the AC voltage signal and a second signal representative of an AC current signal. The first and second signals may be combined with a clock signal to produce a third signal. A phase angle between the AC voltage signal and the AC current signal may be determined based on a pulse count indicative of how many pulses occur in the third signal over a predetermined period of time.

Provided is a counter unit capable of supporting any output apparatus of single-phase output, two-phase output, or three-phase output without waste. A counter unit (10) is provided with: a plurality of signal input terminals to which pulse signals outputted from a plurality of external output apparatuses (50) are respectively inputted; input circuits (21a to 21f) respectively connected to the plurality of signal input terminals; a single-phase counter (13) that performs count on the basis of a single-phase pulse signal, and a multi-phase counter (15) that performs count on the basis of a multi-phase pulse signal; and a switching part (16) that switches whether the input circuits (21a to 21f) are connected to the single-phase counter (13) or the multi-phase counter (15).

Provided is a counter unit capable of supporting any output apparatus of single-phase output, two-phase output, or three-phase output without waste. A counter unit (10) is provided with: a plurality of signal input terminals to which pulse signals outputted from a plurality of external output apparatuses (50) are respectively inputted; input circuits (21a to 21f) respectively connected to the plurality of signal input terminals; a single-phase counter (13) that performs count on the basis of a single-phase pulse signal, and a multi-phase counter (15) that performs count on the basis of a multi-phase pulse signal; and a switching part (16) that switches whether the input circuits (21a to 21f) are connected to the single-phase counter (13) or the multi-phase counter (15).

Provided is a counter unit capable of supporting any output apparatus of single-phase output, two-phase output, or three-phase output without waste. A counter unit (10) is provided with: a plurality of signal input terminals to which pulse signals outputted from a plurality of external output apparatuses (50) are respectively inputted; input circuits (21a to 21f) respectively connected to the plurality of signal input terminals; a single-phase counter (13) that performs count on the basis of a single-phase pulse signal, and a multi-phase counter (15) that performs count on the basis of a multi-phase pulse signal; and a switching part (16) that switches whether the input circuits (21a to 21f) are connected to the single-phase counter (13) or the multi-phase counter (15).

Provided is a counter unit capable of supporting any output apparatus of single-phase output, two-phase output, or three-phase output without waste. A counter unit (10) is provided with: a plurality of signal input terminals to which pulse signals outputted from a plurality of external output apparatuses (50) are respectively inputted; input circuits (21a to 21f) respectively connected to the plurality of signal input terminals; a single-phase counter (13) that performs count on the basis of a single-phase pulse signal, and a multi-phase counter (15) that performs count on the basis of a multi-phase pulse signal; and a switching part (16) that switches whether the input circuits (21a to 21f) are connected to the single-phase counter (13) or the multi-phase counter (15).

The present invention provides an apparatus and method enabling to perform a 2-dimensional trajectory analysis applicable for a three-phase system. A signal analysis apparatus generates a three-row and N-column waveform matrix constituted by three N dimensional row vectors having respectively N samples of first to third phase current values obtained from three-phase current signals measured in a three-phase system, where N is the number of samples of each of the three-phase current signals in one cycle of an AC power supply; applies transformation to the waveform matrix to obtain a two-row and N-column matrix constituted by the first and second N dimensional row vectors; performs normalization in amplitude of the first and second N dimensional row vectors, respectively; selects a grid size based on the sample number N; and maps a two dimensional trajectory made up from the first and second normalized N dimensional row vectors on a grid with the grid size selected.

The present invention provides an apparatus and method enabling to perform a 2-dimensional trajectory analysis applicable for a three-phase system. A signal analysis apparatus generates a three-row and N-column waveform matrix constituted by three N dimensional row vectors having respectively N samples of first to third phase current values obtained from three-phase current signals measured in a three-phase system, where N is the number of samples of each of the three-phase current signals in one cycle of an AC power supply; applies transformation to the waveform matrix to obtain a two-row and N-column matrix constituted by the first and second N dimensional row vectors; performs normalization in amplitude of the first and second N dimensional row vectors, respectively; selects a grid size based on the sample number N; and maps a two dimensional trajectory made up from the first and second normalized N dimensional row vectors on a grid with the grid size selected.

The present disclosure relates to phase measurement circuitry operable based on a first clock signal having an intended clock frequency F1 and a second clock signal having an intended clock frequency F2, the circuitry comprising: a delay line configured to receive the first clock signal, the delay line comprising a plurality of delay units each configured to cause a propagation delay, and the plurality of delay units connected in series along the length of the delay line and defining a series of positions therebetween through which signal edges of the first clock signal propagate over time; an edge detector configured to sample the delay line at successive sample times based on the second clock signal and to record at each sample time the position of a given signal edge of the first clock signal along the delay line; and a phase angle determiner configured to determine a phase angle per delay unit based on successive recorded said positions.

The present disclosure relates to phase measurement circuitry operable based on a first clock signal having an intended clock frequency F1 and a second clock signal having an intended clock frequency F2, the circuitry comprising: a delay line configured to receive the first clock signal, the delay line comprising a plurality of delay units each configured to cause a propagation delay, and the plurality of delay units connected in series along the length of the delay line and defining a series of positions therebetween through which signal edges of the first clock signal propagate over time; an edge detector configured to sample the delay line at successive sample times based on the second clock signal and to record at each sample time the position of a given signal edge of the first clock signal along the delay line; and a phase angle determiner configured to determine a phase angle per delay unit based on successive recorded said positions.