A method for calibrating crosstalk errors in a system for measuring on-wafer S parameters and an electronic device are provided. The method includes two parts. The first part is the pre-calibration part, which obtain eight error terms of an on-wafer S parameter measurement system by using a thru calibration standard, two defined load calibration standards, two pairs of undefined reflect calibration standards, and the reciprocity properties of a passive reciprocal element. The first part performs pre-calibration on an uncalibrated system according to the eight error terms. The second part uses the pre-calibrated system to obtain the crosstalk errors of the measurement system, and performs a further calibration on the pre-calibrated system according to the crosstalk errors.

Disclosed herein are unitary printed circuit boards (PCBs) and methods of using them for testing an integrated circuit (IC). In some embodiments, a unitary PCB comprises a main board portion and a flexible PCB portion, which are configured to be detached from each other at a separation location on the unitary PCB. The main board portion comprises a plurality of pads, and the flexible PCB portion comprises a plurality of through-holes, where a layout of the through-holes corresponds to a layout of the plurality of pads. In some embodiments, a method of testing an IC of a device comprises separating the unitary PBC into a main board portion and a flexible PCB portion, attaching the IC to the main board portion, soldering the main board portion to a platform PCB of the device, and attaching the flexible PCB portion to the main board portion.

Probe cards for probing highly-scaled integrated circuits are provided. A probe card includes a backplane and an array of probes extending from the backplane. Each of the probes includes a cantilever member and a probe tip. A first end of the cantilever member is coupled to the backplane, such that the cantilever member extends from the backplane. The probe tip extends from a second end of the cantilever member. The probes are fabricated from semiconductor materials. Each probe is configured to transmit electrical signals between the backplane and a device under test (DUT), via corresponding electrodes of the DUT. The probes are highly-scaled such that the feature size and pitch of the probes matches the highly-scaled feature size and pitch of the DUT's electrodes. The probes comprise atomic force microscopy (AFM) probes that are enhanced for increased electrical conductivity, elasticity, lifetime, and reliability.

A remote control device testing environment evaluates operational performance of physical implementations of remote control devices. This operational performance of the physical implementations of the remote control devices allows the integrated circuits of the remote control devices as well as integrated circuit interfaces electrically coupling these integrated circuits to each other to be evaluated. Additionally, the interconnection, such as electrical coupling to provide an example, between these integrated circuits and/or the integrated circuit interfaces can be evaluated which otherwise would not be evaluated by software simulation alone. Moreover, the evaluating of this operational performance of the physical implementations of the remote control devices allows these remote control devices to be in evaluated in a real world environment with exposure to various environmental factors, such as temperature, humidity, and/or electromagnetic interference to provide some examples. Furthermore, the evaluating of this operational performance of the physical implementations of the remote control devices allows interactions between these remote control devices and other electronic devices to be evaluated.

An integrated circuit (IC) test engine can generate a plurality of single cycle test patterns that target a plurality of static single cycle defects of a fabricated IC chip based on an IC design. The IC test engine can also fault simulate the plurality of single cycle test patterns against a plurality of multicycle defects in the IC design, wherein a given single cycle test pattern of the plurality of single cycle test patterns is sim-shifted to enable detection of a given multicycle fault and/or defect of the plurality of multicycle faults and/or defects.

A method is provided in the present disclosure. The method includes several operations: generating, by a processing unit, a mapping table associated with multiple scan chains and multiple shift cycles corresponding to multiple values stored in the scan chains in an integrated circuit; determining, based on the mapping table, at least one fail flip flop in the scan chains in response to the values outputted from the scan chains; and identifying at least one fault site corresponding to the at least one fail flip flop.

A thermal management system for a test-and-measurement probe that includes a thermally insulated shroud and a fluid inlet conduit. The shroud is configured to enclose a first portion of a probe head of the probe within an interior cavity of the shroud, while permitting a second portion of the probe head to extend out of the shroud. The shroud further includes a fluid outlet passageway configured to permit a heat-transfer fluid to pass from a probe-head end of the interior cavity, through the interior cavity of the shroud, and out of the shroud through an access portion of the shroud. The fluid inlet conduit enters the shroud through the access portion of the shroud, extends through the interior cavity of the shroud, and is configured to introduce the heat-transfer fluid to the probe-head end of the interior cavity.

A testing holder for a chip unit, a multi site holding frame for plural chip units and a method for testing a die thereof are provided. The proposed multi site holding frame for testing plural chip units simultaneously includes a first holder frame having a plurality of testing holders. Each of the plurality of testing holders includes a holder body containing a specific one of the plural chip units, and a pressure releasing device formed on the holder body to release an insertion pressure when the specific one of the plural chip units is inserted in the holder body.

An inspection apparatus includes a light sensor that detects light from a semiconductor device to which an electric signal has been input, an optical system that guides light from the semiconductor device to the light sensor, and a control device electrically connected to the light sensor. The control device includes a measurement unit that acquires waveform data obtained by optical measurement for each of a plurality of positions on a defective semiconductor device and waveform data obtained by the optical measurement for each of a plurality of positions on a non-defective semiconductor device, a calculation unit that calculates a degree of correspondence between the waveform data of the defective semiconductor device and the waveform data of the non-defective semiconductor device, and an analysis unit that analyzes a defective part of the defective semiconductor device on the basis of the degree of correspondence for each of the plurality of positions.

A test board configured to test a device under test includes: a connection region including first and second connection terminals for contacting the device under test; and a first surface mount device located adjacent to the connection region, wherein the first connection terminal is configured to be electrically connected to a first voltage regulator of the device under test, wherein the second connection terminal is configured to be electrically connected to a second voltage regulator of the device under test, and wherein the first surface mount device is configured to be electrically connected to each of the first and second connection terminals.