Patent classifications
G01R31/28
TEST APPARATUS FOR TEST CARDS
A test apparatus (1) for test cards (37), comprising a receiving device (3) for holding at least one test card (37) to be tested, comprising at least one contact device (4) for making electrical touch contact with electrically conductive contact points of the at least one test card (37) in the receiving device (3), wherein the contact device (4) can be arranged vertically above the receiving device for the purpose of making touch contact, and comprising an actuating device (19), which is formed to displace the contact device (4) and the receiving device (3) relative to one another for the purpose of establishing the touch contact. It is provided that the receiving device (3) can be displaced by means of the actuating device (19) from a test position, which is located vertically below the contact device (4), into a loading and unloading position, which is laterally spaced apart from the contact device (4), and the other way round.
Single-Event Transient (SET) Pulse Measuring Circuit Capable of Eliminating Impact Thereof, and Integrated Circuit Chip
The present disclosure discloses a Single-Event Transient (SET) pulse measuring circuit capable of eliminating impact thereof, and an integrated circuit chip. The SET pulse measuring circuit capable of eliminating impact thereof includes four parts: a SET pulse test chain, a latch circuit, a flip-flop test circuit, a latching self-trigger circuit. The integrated circuit chip is provided with a test chain module and two sets of SET pulse measuring circuits capable of eliminating impact thereof, and inputs of the two sets of SET pulse measuring circuits capable of eliminating impact thereof are the same and each are connected to an output terminal of the test chain module.
ELEVATOR UNIT FOR TRANSFERRING TRAY AND TEST HANDLER INCLUDING SAME
An elevator unit for transferring a tray includes a tray guide block on which a tray is seated, a wrapping connector driving member configured to elevate and lower the tray guide block, a fixed fastener connected to the tray guide block, and a corrective fastener connected to the wrapping connector driving member and configured to rotatably coupled to the fixed fastening member.
Multi-input multi-zone thermal control for device testing
Disposing a DUT between a cold plate and an active thermal interposer device of the thermal management head. The DUT includes a plurality of modules and the active thermal interposer device includes a plurality of zones, each zone of the plurality of zones corresponding to a respective module of the plurality of modules and operable to be selectively heated. Receiving a respective set of inputs corresponding to each zone of the plurality of zones. Performing thermal management of the plurality of modules of the DUT by separately controlling temperature of each zone of the plurality zones by controlling a supply of coolant to a cold plate, and individually controlling heating of each zone of the plurality zones.
Quantum error-correction in microwave integrated quantum circuits
In a general aspect, a quantum error-correction technique includes applying a first set of two-qubit gates to qubits in a lattice cell, and applying a second, different set of two-qubit gates to the qubits in the lattice cell. The qubits in the lattice cell include data qubits and ancilla qubits, and the ancilla qubits reside between respective nearest-neighbor pairs of the data qubits. After the first and second sets of two-qubit gates have been applied, measurement outcomes of the ancilla qubits are obtained, and the parity of the measurement outcomes is determined.
Unified approach for improved testing of low power designs with clock gating cells
An apparatus includes a core logic circuit, one or more integrated clock-gating (ICG) cells, and one or more ICG control cells (ICCs). The core logic circuit generally comprises a plurality of flip-flops. The plurality of flip-flops may be connected to form one or more scan chains. Each of the one or more integrated clock-gating (ICG) cells may be configured to gate a clock signal of a respective one of the one or more scan chains. Each of the one or more ICG control cells may be configured to control a respective one or more of the one or more ICG cells.
System and method for testing radiation susceptibility capable of simulating impact of a radiation wave to a device under test
Abstract of Disclosure A method for testing radiation susceptibility includes transmitting radiation wave to a device under test, measuring the device under test to generate a first voltage according to the radiation wave, outputting a reference voltage to a coupling device so that the coupling device generates a second voltage according to the reference voltage, adjusting the reference voltage so that the second voltage approximates the first voltage, storing the adjusted reference voltage, outputting the second voltage to the device under test according to the adjusted reference voltage to simulate an impact of the radiation wave to the device under test, the device under test accordingly transmitting a control signal to the coupling device after receiving the second voltage, and determining a status of the device under test according to the control signal.
Method of preparing composite material for semiconductor test socket that is highly heat-dissipative and durable, and composite material prepared thereby
This application relates to a method of preparing a composite material for a semiconductor test socket, and a composite material prepared through the method. In one embodiment, the method includes preparing a powder mixture including (i) a metal powder comprising aluminum or aluminum alloy particles and magnesium particles and (ii) a polymer powder. The method may also include sintering the powder mixture to produce the composite material using a spark plasma sintering (SPS) process. This application also relates to a method of manufacturing a semiconductor test socket, the method including forming an insulating portion of the semiconductor test socket with the composite material. This application further relates to a semiconductor test socket produced through the method.
Test handler having multiple testing sectors
A test handler comprising a primary rotary turret comprising pick heads for transporting electronic components, and a secondary rotary turret arranged and configured to receive electronic components directly or indirectly from the primary rotary turret, the secondary rotary turret including multiple separate test sectors having component carriers for carrying the electronic components received from the primary rotary turret, wherein the multiple test sectors are rotatably movable relative to one another. The test handler also comprises at least one testing device positioned along a periphery of the secondary rotary turret, wherein the component carriers of the respective test sectors are operative to convey the electronic components to a position of the at least one testing device for testing.
Impedance tuners with linear actuators
The accuracy of an impedance tuner may be improved and the size may be reduced by using linear actuators instead of rotary motors. The linear actuator may be integrated with position sensors to allow very small size, and implemented with a servo system for best accuracy and speed. Spring loaded arms holding the mismatch probes allow the tuner to operate in any orientation to further fit into small spaces. The small size reduces losses by allowing direct connection to wafer probes for on-wafer measurement systems.