Embodiments of the present disclosure disclose a display panel, which includes a cover plate, a pixel layer, and a driving circuit layer. The driving circuit layer is disposed between the cover plate and the pixel layer. The driving circuit layer includes a metal layer and a darkening layer, the darkening layer is disposed on a side of the metal layer towards the cover plate, and a reflectivity of the darkening layer of external light is less than a reflectivity of the metal layer of the external light. When the external light is irradiated, the reflectivity of the darkening layer is less; therefore rainbow mura generated when the external light source illuminates the display panel.

The present disclosure relates to a display device, and more particularly, a display device comprises: a plurality of light sources; a resin layer disposed to cover the plurality of light sources; and a display panel disposed on the resin layer and including a display area and a non-display area, wherein the resin layer comprises: a first region configured to overlap the display area; and a second region configured to overlap the non-display area, and wherein a plurality of fine holes are provided in at least a part of the second region. Therefore, the decomposed materials, which are produced by the decomposition of the backlight unit and the components around the backlight unit in a high-temperature, high-humidity environment, may be discharged through the fine holes.

An active IR camouflage device may include a base layer, a first dielectric layer over the base layer, a phase transition material layer over the first dielectric layer, a second dielectric layer over the phase transition material layer, and a first metal layer over the second dielectric layer and defining a pattern of openings therein. The active IR camouflage device may have circuitry configured to selectively cause a transition from a first phase state to a second phase state of the phase transition material layer to control IR reflectance/emission of a top plasmonic layer, making it appear/disappear from the IR detector/camera. In some embodiments, the active IR camouflage device may also include a second metal layer between the base layer and the first dielectric layer.

An active matrix substrate includes a first pixel region defined by first and second source bus lines adjacent to each other and first and second gate bus lines adjacent to each other and further includes a first pixel electrode and a first oxide semiconductor TFT that are associated with the first pixel region. The first oxide semiconductor TFT includes an oxide semiconductor layer and a gate electrode electrically connected to the first gate bus line. The oxide semiconductor layer includes a channel region and a low-resistance region including first and second regions located on opposite sides of the channel region. When viewed in a direction normal to the substrate, the low-resistance region extends across the first source bus line to another pixel region and partially overlaps a pixel electrode disposed in the other pixel region with an insulating layer interposed therebetween.

A display panel for displaying an image is provided with a plurality of pixels arranged in a matrix. Each pixel includes one or more units each including a purality of subunits. Each subunit includes a transistor in which an oxide semiconductor layer which is provided so as to overlap a gate electrode with a gate insulating layer interposed therebetween, a pixel electrode which drives liquid crystal connected to a source or a drain of the transistor, a counter electrode which is provided so as to face the pixel electrode, and a liquid crystal layer provided between the pixel electrode and the counter electrode. In the display panel, a transistor whose off current is lower than 10 zA/.Math.m at room termperature per micrometer of the channel width and off current of the transistor at 85° C. can be lower than 100 zA/.Math.m per micrometer in the channel width.

An FFS mode array substrate and a manufacturing method thereof are provided. The FFS mode array substrate has: a second insulation layer deposited on a base layer, wherein a first through hole and a second through hole are formed in the second insulation layer; a pixel electrode layer deposited on the second insulation layer, wherein the pixel electrode layer is provided with a plurality of pixel electrodes; and a third insulation layer formed on a source electrode, a drain electrode, the pixel electrodes, and the second insulation layer.

Provided is a semiconductor device having a top-gate structure resistant to creation of parasitic capacitance between a low-resistance region formed in a semiconductor layer and a gate electrode, and also provided region method for manufacturing the same and a display device including the same.

A TFT (100) has a low-resistance region, a portion of which has a first length (L1) ranging from a first position (P1) corresponding to an end of a gate insulating film to a region below a gate electrode (40), and the first length is substantially equal to a second length (L2) ranging from the first position (P1) to a second position (P2) corresponding to an end of the gate electrode (40). Thus, the overlap between the gate electrode (40) and either a source region (20s) or a drain region (20d) can be reduced, resulting in diminished parasitic capacitance.

A first substrate of a display device includes a TFT provided for each pixel and including an oxide semiconductor layer. A second substrate includes a color filter layer and a light blocking layer. At least one of a first, second and third color filter included in the color filter layer has an average transmittance of 0.2% or less for visible light having a wavelength of 450 nm or less. In pixels provided with color filters having an average transmittance of 0.2% or less for visible light having a wavelength of 450 nm or less, the light blocking layer (a) includes a TFT shading portion extending along a channel length direction and having a width that is less than or equal to a length of the oxide semiconductor layer along a channel width direction; (b) includes a TFT shading portion extending along the channel width direction and having a width that is less than or equal to the length of the oxide semiconductor layer along the channel length direction; or (c) includes no TFT shading portion.

To improve the display quality of a display device. To display a high-quality video regardless of a usage environment. To provide a light-weight and non-breakable display device. To reduce power consumption of a display device. The display device includes a first display element, a second display element, a light diffusion plate, and a polarizing plate. The first display element is a reflective liquid crystal element. The second display element is configured to emit visible light. The light diffusion plate and the polarizing plate are closer to a display surface side than the first display element is. The display device is configured to display an image using one or both of first light reflected by the first display element and second light emitted by the second display element.

A light emission module includes a laser source, a beam steering element and a scanning-angle expanding lens set. The laser source is used for emitting a laser beam. The beam steering element is used for receiving the laser beam and splitting the laser beam into at least two laser beams. The scanning-angle expanding lens set, adjacent to the beam steering element, is configured to receive and integrate the at least two laser beams, and to control a spanning angle and a scanning angle between the at least two laser beams on a scanned object. The spanning angle is a visual angle of a vertical scan direction of the scanned object, and the scanning angle is another visual angle of a horizontal scan direction of the scanned object. In addition, a light emission module and a light scanning method are also provided.