In a method of manufacturing a chemical fluid for manufacturing an electronic material, a method of reducing particulate metal in the chemical fluid is selected according to a concentration of particulate metal including an iron atom, a concentration of particulate metal including a copper atom, and a concentration of particulate metal including a zinc atom which are measured by SP ICP-MS in the chemical fluid, and at least one of the concentration of particulate metal including an iron atom, the concentration of particulate metal including a copper atom, or the concentration of particulate metal including a zinc atom is reduced by using the selected reducing method.

Provided are a method and apparatus for cleaning organic materials accumulated on a mask used in a process of depositing organic materials. The apparatus includes a plasma generating unit, a cleaning chamber connected to the plasma generating unit and accommodating the mask therein, a gas injection port disposed within the cleaning chamber configured to inject the plasma, and a cooling device disposed on a first surface of the mask opposite to an opposite surface of the mask facing the gas injection port.

A method for the simulation of a photolithographic process for generating a wafer structure includes providing an aerial image of a region of a mask that includes the mask structure, prescribing a range of intensities, determining auxiliary or potential wafer structures for different threshold values within the range of intensities, determining the number of structure elements for each of the auxiliary or potential wafer structures, determining a stability range consisting of successive threshold values from the threshold values that were used for the determination of auxiliary or potential wafer structures, within the stability range the number of structure elements of the auxiliary or potential wafer structures remaining constant or lying within a prescribed range, and determining the wafer structure on the basis of the aerial image and a threshold value within the stability range. A microscope for carrying out the method is also provided.

A method comprises receiving an integrated circuit (IC) chip design, and generating, by one or more processors, a wafer image and a wafer target from the IC chip design. The method further comprises generating, by the one or more processors, sensitivity information based on a determination that the wafer image and the wafer target converge, and outputting the sensitivity information. The sensitivity information is associated with writing a mask written for the IC chip design.

According to a first aspect of the present invention, there is provided a method, a computer system and a computer program product. The method, computer system and computer program product including measuring an initial state of a set of SRAM bits on the wafer, identifying a first set of signature SRAM bits on the wafer, of the set of SRAM bits on the wafer, where the first set of SRAM bits comprise a consistent initial state greater than a first threshold percentage of times, measuring physically dimensions of features of the first set of SRAM bits on the wafer; and identifying a set of signature SRAM bits of the first set of SRAM bits on the wafer, wherein the set of signature SRAM bits comprise physical dimensions of features which correlate to the initial state of each correlated SRAM bit.

A photomask and a method of forming the same, the photomask including a transparent substrate; a light shielding pattern on the transparent substrate, the light shielding pattern including molybdenum and silicon; and an etch stop layer covering at least a sidewall of the light shielding pattern, wherein the etch stop layer has an etch rate lower than an etch rate of the light shielding pattern with respect to an ammonia-based cleaning solution.

A photomask and a method of forming the same, the photomask including a transparent substrate; a light shielding pattern on the transparent substrate, the light shielding pattern including molybdenum and silicon; and an etch stop layer covering at least a sidewall of the light shielding pattern, wherein the etch stop layer has an etch rate lower than an etch rate of the light shielding pattern with respect to an ammonia-based cleaning solution.

The present invention relates generally to the technical field of integrated circuit mask design, and more particularly to a method, an apparatus and an electronic device for Hessian-Free photolithography mask optimization. The method includes steps: S1, inputting a design layout of a mask to be optimized; S2, positioning error monitoring points on the design layout of the mask to be optimized; S3, obtaining an optimization variable x of the mask to be optimized; S4, forming an objective function cost on the optimization variable x; and S5, optimizing the objective junction cost by a Hessian-Free-based conjugate gradient method, to obtain an optimization result of the mask to be optimized. Optimizing the objective function cost based on a Hessian-Free conjugate gradient method to obtain an optimization result of the mask to be optimized, which can greatly reduce the computation resources in the optimization process, make the optimization process simpler, feasible, and improve the optimization efficiency. Meanwhile, there is no need to use the quasi-Newton method to obtain the approximate replacement matrix of the H matrix, which can improve the accuracy of the optimization result.

The present invention refers to a method for performing an aerial image simulation of a photolithographic mask which comprises the following steps: (a) modifying an optical radiation distribution at a patterned surface of the photolithographic mask, depending on at least one first arrangement of pixels to be generated in the photolithographic mask; and (b) performing the aerial image simulation of the photolithographic mask by using the generated modified optical radiation distribution.

In a method of manufacturing a semiconductor device, an initial pattern layout is obtained. The initial pattern layout incudes fin patterns which include active fin patterns to be formed as active fin structures and dummy fin patterns not to be formed as actual fin structures or to be removed. The locations of the fin patterns are modified, as follows. A space between adjacent active fin patterns is increased by a first amount, a space between the dummy fin patterns is decreased by a second amount, and a space between one of the dummy fin patterns and one of the active fin patterns adjacent to the one of the dummy fin patterns is decreased by a third amount. Mandrel patterns are placed so that the fin patterns of which locations are modified are placed along longitudinal edges of the mandrel patterns.