Technologies are provided for time-to-digital conversion without reliance on a clocking signal. Some embodiments of the technologies include a clockless TDC apparatus that can map continuous pulse-widths to binary bits represented via an iterative chaotic map (e.g., tent map, Bernoulli shift map, or similar). The clockless TDC apparatus can convert separated pulses to a single asynchronous digital pulse that turns on when a sensor detects a first pulse and turns off when the sensor detects a second pulse. The asynchronous digital pulse can be iteratively stretched and folded in time according to the chaotic map. The clockless TDC can generate a binary sequence that represents symbolic dynamics of the chaotic map. The process can be implemented by using an iterative time delay component until a precision of the binary output is either satisfied or overwhelmed by noise or other structural fluctuations of the TDC apparatus.

A real-time clock device includes a resonator, a clock signal generation circuit, a time-counting circuit, a terminal, and a time-to-digital conversion circuit. The clock signal generation circuit outputs a time-counting clock signal based on an oscillation clock signal. The time-counting circuit generates time-counting data based on the time-counting clock signal. An external signal is input to the terminal. The time-to-digital conversion circuit measures a time difference between a transition timing of a first signal based on the external signal and a transition timing of a second signal based on the oscillation clock signal or the time-counting clock signal with a resolution higher than a time-counting resolution of the time-counting circuit, and obtains time difference information corresponding to the time difference.

A digital phase-locked loop (DPLL) may include a time-to-digital converter (TDC) to provide a phase error signal, a frequency-divider to perform frequency division on an output signal to generate a frequency-divided output signal, a delta-sigma-modulator (DSM) to provide a test signal that represents a quantization error of the DSM, and a digital-to-time converter (DTC) to at least partially remove the quantization error from the frequency-divided output signal based on the test signal to generate the feedback signal. The DPLL may include a circuit to cause the DTC to provide a percentage of the quantization error such that the percentage of the quantization error is in the phase error signal, and a TDC calibration component to calibrate the TDC by applying a gain adjustment factor to the TDC. The gain adjustment factor may be based on the test signal and the phase error signal including the percentage of the quantization error.

A clock product includes a time-to-digital converter responsive to an input clock signal, a reference clock signal, and a time-to-digital converter calibration signal. The time-to-digital converter includes a coarse time-to-digital converter and a fine time-to digital converter. The clock product includes a calibration circuit including a phase-locked loop. The calibration circuit is configured to generate the time-to-digital converter calibration signal. The clock product includes a controller configured to execute instructions that cause the phase-locked loop to generate an error signal for each possible value of a fine time code of a digital time code generated by the time-to-digital converter and to average the error signal over multiple clock cycles to generate an average error signal.

A frequency determination device for determining a frequency relationship between a reference signal and a clock signal. Each constituent TDC is configured to provide a digitally represented constituent output signal in response to receiving a constituent reference signal and a constituent clock signal, and the frequency determination device is configured to successively provide respectively delayed versions of the constituent clock signal of a first constituent TDC as respective constituent clock signals to the other constituent TDC:s. The reference signal provider is configured to provide the respective constituent reference. The switching circuitry is configured to provide the reference signal as the constituent clock signal to the first constituent TDC. The determination circuitry is configured to determine a number of consecutively same-valued symbols in a concatenation of the digitally represented constituent output signals of the constituent TDC:s, and to determine the frequency relationship.

A time-to-digital converter (TDC) that combines the energy efficiency of a successive approximation (SAR) design with the high speed of pipelined converters by leveraging the inherently pipelined nature of time-domain signaling. The TDC achieves high speed by removing a comparator decision from a signal path, instead using AND/OR gates to separate early and late edges. The TDC uses a pipelined SAR architecture to digitize a differential delay between two incoming clock edges with high speed and low power consumption. Described is a modular digital reference voltage generator that can be used for a capacitive digital-to-analog converter (DAC). The generator comprises a decoupling capacitor, one or more clocked comparators, and power transistor(s). A simplified digital low dropout (LDO) circuitry is used to provide fast reference voltage generation with minimal overhead. The LDO circuitry is arrayed using time-interleaved synchronous clocks or staggered asynchronous clocks to provide finer timing resolution.

A digital-to-time converter (DTC) and methods of calibrating the same reduces or mitigates nonlinearity and thus improves DTC performance. A slope of a voltage signal of the DTC is calibrated using a capacitor and a comparator. Capacitance of the capacitor and/or maximum current of a current source is adjusted to configure the comparator to output a signal during a second phase when a reference voltage signal is at or above a first level and below a second level. Calibrating gain of the DTC includes adjusting a time difference between an output signal of the DTC set at a first digital code value and the output signal of the DTC set at a second digital code value to be one period of a clock signal input to the DTC. Calibrating integral nonlinearity of the DTC includes measuring a time period for each of multiple digital code values of the DTC.

The Digital Time Processing using Rational Number Filters (DTP RNF) disclosed herein is contributing methods, systems and circuits for using a Precision Time Protocol (PTP) such as IEEE 1588 for distributing a master time secured by a master unit to slave units by utilizing slave clocks, synchronous to referencing frames communicated with PTP messages or compatible with them data receiver clocks, for maintaining a local slave time which is increased to a local master time by adding to it an estimate of a transmission delay derived by processing PTP messages or by other means, wherein such distribution of the master time includes filtering out phase noise of the timing referencing signals with the Rational Number Filters in order to produce accurate and stable timing implementing signals such as the slave clock, local slave time and local master time.

Systems, methods, and devices are provided for a circuit for generating a pulse output having a controllable pulse width. Systems and methods may include a delay line having a plurality of stages. A delay per stage calculation circuit is configured to determine a per-stage delay of the delay line using a first clock input. A pulse generation circuit is configured to generate the pulse output using the delay line based on the per-stage delay using a second clock input, the second clock input having a lower frequency than the first clock input.

A circuit is disclosed. The circuit includes a time-to-digital converter (TDC), and an evaluation circuit coupled to the TDC and a phase-locked loop (PLL) external to the circuit.