The Digital Time Processing over Time Sensitive Networks (DTP TSN) disclosed herein is contributing methods, systems and circuits for using a Precision Time Protocol (PTP) such as IEEE 1588 for distributing a master time secured by a master unit to slave units by utilizing slave clocks recovered from PTP messages and/or compatible with them data receiver clocks for maintaining a local slave time which is increased to a local master time by adding to it an estimate of a transmission delay derived by processing PTP messages, wherein such distribution of the master time includes filtering out phase noise of a timing referencing signals communicated by PTP messages in order to produce accurate timing implementing signals such as the slave clock, local slave time and local master time.

A system delays input clock signals using time-to-digital converters (TDCs) to convert edges or the clock signals to digital values and storing the digital values in a memory. The digital values are retrieved from the memory based on a desired delay. A time counter used by the TDCs to determine the edges is also used determine the delay. The accuracy and range of the delay depends on the time counter and size of the memory.

Methods and apparatus for an arrayed time to digital converter (TDC) having matched delay line sampling. In embodiments, a TDC includes a coarse counter circuit to provide an event coarse timing measurement for an event, a coarse counter delivery network to deliver a count value in the coarse counter circuit to a memory storage element circuit, and an array of matched delay lines to provide an event fine timing measurement to the memory storage element circuit. An array of event sample signal generators can generate signals for the event and an array of encoders can encode fine timing measurement information from the memory storage element circuit, where an output of the encoder and the event coarse timing measurement information provide a timestamp for the event. A global delay-locked loop can incorporate a matched delay line coupled to the array of matched delay lines.

Time-to-digital converter arrangement having a first and a second time-to-digital converters. The first one is configured to determine the existence or nonexistence of an event in a recurring first measurement window. The second one is configured to determine the existence or nonexistence of the event in a recurring second measurement window. A temporal relation of the second measurement window with respect to detecting the event is time-shifted by a first offset compared to a temporal relation of the first measurement window with respect to detecting the event.

A delay selector includes a first multiplexer, a first inverter, a second multiplexer, and a second inverter. The first multiplexer has a first input coupled to an input of the delay selector. The first inverter is coupled between the input of the delay selector and a second input of the first multiplexer. The second multiplexer has a first input coupled to an output of the first multiplexer. The second inverter is coupled between the output of the first multiplexer and a second input of the second multiplexer.

Various embodiments of the present technology may provide methods and apparatus for repetitive histogramming. The apparatus may provide a limited number of physical bins to perform multiple histograms on a total number of virtual bins. The apparatus may provide a single physical bin that is used to sweep over the total number of virtual bins.

A controller includes a phase frequency detection circuit which has a first input coupled to receive a reference clock input, a second input coupled to receive a high-side active output, and an output configured to provide a PFD output. The controller includes a control loop filter which has a first input coupled to receive a slew rate input, a second input coupled to receive the PFD output, and an output configured to provide a high-side length output. The controller includes a pulse generation circuit which has a first input coupled to receive the high-side active output, a second input coupled to receive the high-side length output, and an output configured to provide a fine pulse output. The controller includes a latch configured to provide the high-side active output responsive to a comparison output and the fine pulse output.

Provided herein are delay locked loops (DLLs) with calibration for external delay. In certain embodiments, a timing alignment system includes a DLL including a detector that generates a delay control signal based on comparing a reference clock signal to a feedback clock signal, and a controllable delay line configured to generate the feedback clock signal by delaying the reference clock signal based on the delay control signal. The timing alignment system further includes a delay compensation circuit that provides an adjustment to the controllable delay line to compensate for a delay of the feedback clock signal in reaching the detector.

A depth camera assembly (DCA) includes a direct time of flight system for determining depth information for a local area. The DCA includes an illumination source, a camera, and a controller. The illumination source projects light (e.g., pulse of light) into the local area. The camera detects reflections of the projected light from objects in the local area. Using an internal gating selection procedure, the controller selects a gate window that is likely to be associated with reflection of a pulse of light from an object. The selected gate may be used for depth determination. The internal gating selection procedures may be achieved through external target location and selection or through internal self-selection.

An N-element baseband (BB) time-domain spatial signal processor system and methodology for large modulated bandwidth multi-antenna receivers are provided. Such a processor generally includes a pipeline converter configured as an asynchronous time-to-digital converter, wherein the asynchronous time-to-digital converter arrangement generates a residue value and an asynchronous pulse and is further arranged to amplify the residue value so as to result in an amplified residue value; and a 2-bit flash time-to-digital-converter configured to quantize the amplified residue value. Thus, a true-time delay spatial signal processing system and technique in the time-domain that enables beamforming, beam-nulling and multiple independent interference cancellation after time-alignment of signals using cascaded voltage-to-time converters and quantization using relaxed pipeline time-to-digital converters is presented.