Various embodiments of the present technology may provide methods and apparatus for a time-to-digital converter. The time-to-digital converter may include a state machine that increments/decrements according to an input signal and a count value. The time-to-digital converter may further include a register to store the count value according to the input signal.

A waveform capture device (WCD) is a flexible measurement system capable of recording complex digital signals on trillionth-of-a-second (ps) time scales. The WCD may be implemented via modular code on an off-the-shelf field-programmable gate-array (FPGA), and incorporates both time-to-digital converter (TDC) and digital storage oscilloscope (DSO) functionality. The device captures a waveform by taking snapshots of a signal as it propagates down an ultra-fast transmission line known as a carry chain (CC). It may be calibrated via a dynamic phase-shifting (DPS) method that requires substantially less data and resources than conventional techniques.

Disclosed are a soil monitoring sensor and a method of operating the same. The soil monitoring sensor includes a first probe formed to extend in a first direction, and including a first electrode and a second electrode; a first resonance circuit connected to the first electrode and the second electrode of the first probe, and configured such that a first AC signal is applied thereto; a second resonance circuit having the same impedance as the first resonance circuit, and configured such that a second AC signal is applied thereto; and a determination circuit configured to receive a first electrical signal formed in the first resonance circuit, to receive a second electrical signal formed in the second resonance circuit, and to generate a first determination value for the state of the soil based on the first resonant frequency and the second resonant frequency.

A circuit is disclosed. The circuit includes a time-to-digital converter (TDC), and an evaluation circuit coupled to the TDC and a phase-locked loop (PLL) external to the circuit.

Various embodiments of the present technology may provide methods and apparatus for a time-to-digital converter. The time-to-digital converter may include a state machine that increments/decrements according to an input signal and a count value. The time-to-digital converter may further include a register to store the count value according to the input signal.

An optical receiver includes a parasitic current compensation circuit having a reference diode, a sense avalanche photodiode (APD), at least one DC voltage source, and a measurement node. The at least one DC voltage source is configured to generate a first DC bias voltage that varies over time and drives the reference diode, and generates a second DC bias voltage that varies over time and drives the sense APD. A reference parasitic current travels through the reference diode based on the first DC bias voltage. A sense current travels through the sense APD based on the second DC bias voltage and exposure of the sense APD to a light signal. The measurement node receives a sense photocurrent, which is generated by the sense APD in response to the exposure of the sense APD to the light signal, the sense photocurrent including the sense current less the reference parasitic current.

A circuit device includes an analog front-end circuit that receives a target signal is input, and a processing circuit that performs arithmetic processing based on an output signal from the analog front-end circuit. The analog front-end circuit includes a plurality of comparator circuits that compare the voltage level of the target signal to a plurality of threshold voltages and output a plurality of comparison result signals. The processing circuit obtains the transition timing of the target signal based on the comparison result signals and delayed-time information of the analog front-end circuit.

A delay circuit includes a state transition section configured to start state transition based on a trigger signal and output state information indicating the internal state and a transition-state acquisition section configured to latch and hold the state information. The state transition section includes a tapped delay line in which a plurality of delay elements are coupled, a logical circuit configured to generate a third signal based on a first signal based on the trigger signal and a second signal, which is an output signal of the delay element, and a synchronous transition section configured to count an edge of the third signal. The state information is having an output signal of the synchronous transition section and an output signal of the tapped delay line. A humming distance of the state information before and after the state transition is 1. A time from when the internal state transitions from a first internal state to a second internal state until when the internal state transitions to the first internal state again is longer than an interval of a time for updating the state information held by the transition-state acquisition section.

Provided is a time-to-digital converter, comprising a phase frequency detector configured to receive a phase-locked loop input clock and a feedback clock, a ring oscillator configured to perform oscillation with multi-phase clocks of a first period, a counter array configured to count the number of oscillations in which the ring oscillator oscillates in a first period by the number of positive integers during the first pulse width, a multiplexer configured to divide the first period into a plurality of zones using edge information of the multi-phase clocks of the ring oscillator, and selects and outputs voltage information of a plurality of neighboring phase clocks included in a first zone from the plurality of zones, an analog-to-digital converter, a calibrator, and a first adder, wherein the calibrator comprises, an offset lookup table generation circuit, a gain-corrected analog-to-digital conversion output generator, and a second adder.

To improve power converter ON-time generation, an example apparatus includes: a phase frequency detector to determine a phase difference between a first signal and a second signal; a first pulse generator to generate a first time signal at a second time, in which the first signal is associated with a first time delay based on the phase difference; and a second pulse generator coupled to the first pulse generator. The second pulse generator is configured to: generate a second time signal at a third time, in which the third time is after the second time; and obtain a digital word based on the phase difference at a first time, in which the first time is before the second time and the third time, and the second time signal is associated with a second time delay based on the phase difference.