Patent classifications
G04F10/04
Clock screening with programmable counter-based clock interface and time-to-digital converter with high resolution and wide range operation
A sub-ranging time-to-digital converter (TDC) is disclosed that includes two ring oscillators for determining a time difference between two clock edges.
POWERTRAIN ENGINE CONTROL METHOD AND VEHICLE OPERATED THEREBY
A powertrain engine control method may include: acquiring period information based on tooth information of an engine crank target wheel by using a timer (T); subdividing the period information by a division rate value (R) by using a timer (D) so as to enable the timer (D) to operate R times; carrying out synchronization with the timer (D) and carrying out counting by using a timer (A) from a zero (0) to 720 degrees for a four-stroke engine operation cycle; and correcting, by using a timer (V), an angle counter which is not generated at the time of deceleration of a vehicle.
POWERTRAIN ENGINE CONTROL METHOD AND VEHICLE OPERATED THEREBY
A powertrain engine control method may include: acquiring period information based on tooth information of an engine crank target wheel by using a timer (T); subdividing the period information by a division rate value (R) by using a timer (D) so as to enable the timer (D) to operate R times; carrying out synchronization with the timer (D) and carrying out counting by using a timer (A) from a zero (0) to 720 degrees for a four-stroke engine operation cycle; and correcting, by using a timer (V), an angle counter which is not generated at the time of deceleration of a vehicle.
CLOCK SCREENING WITH PROGRAMMABLE COUNTER-BASED CLOCK INTERFACE AND TIME-TO-DIGITAL CONVERTER WITH HIGH RESOLUTION AND WIDE RANGE OPERATION
A sub-ranging time-to-digital converter (TDC) is disclosed that includes two ring oscillators for determining a time difference between two clock edges.
Clock screening with programmable counter-based clock interface and time-to-digital converter with high resolution and wide range operation
A subranging time-to-digital converter (TDC) is disclosed that includes two ring oscillators for determining a time difference between two clock edges.
Clock screening with programmable counter-based clock interface and time-to-digital converter with high resolution and wide range operation
A subranging time-to-digital converter (TDC) is disclosed that includes two ring oscillators for determining a time difference between two clock edges.
SENSING SYSTEM AND SENSOR DEVICE
To synchronize, in a system in which a plurality of devices perform measurement, measurement timings with each other with a simple configuration. A sensing system includes a plurality of sensor devices. The sensor devices each include a trigger sensor and a target sensor. In the sensor device, the trigger sensor measures a signal value of a trigger signal. Also, in the sensor device, the target sensor starts to measure a physical quantity when the signal value measured by the trigger sensor satisfies a predetermined condition.
SENSING SYSTEM AND SENSOR DEVICE
To synchronize, in a system in which a plurality of devices perform measurement, measurement timings with each other with a simple configuration. A sensing system includes a plurality of sensor devices. The sensor devices each include a trigger sensor and a target sensor. In the sensor device, the trigger sensor measures a signal value of a trigger signal. Also, in the sensor device, the target sensor starts to measure a physical quantity when the signal value measured by the trigger sensor satisfies a predetermined condition.
CLOCK SCREENING WITH PROGRAMMABLE COUNTER-BASED CLOCK INTERFACE AND TIME-TO-DIGITAL CONVERTER WITH HIGH RESOLUTION AND WIDE RANGE OPERATION
A subranging time-to-digital converter (TDC) is disclosed that includes two ring oscillators for determining a time difference between two clock edges.
Comparator, circuit device, physical quantity sensor, electronic device, and vehicle
A comparator includes a first voltage-time conversion circuit, a second voltage-time conversion circuit, and a determination circuit. A first delay unit includes a first falling edge delay circuit that delays a falling edge based on a first input signal, a first rising edge delay circuit that delays a rising edge based on a second input signal, and a first output circuit. A second delay unit includes a second falling edge delay circuit that delays a falling edge based on the second input signal, a second rising edge delay circuit that delays a rising edge based on the first input signal, and a second output circuit.