A comparator includes a first voltage-time conversion circuit, a second voltage-time conversion circuit, and a determination circuit. A first delay unit includes a first falling edge delay circuit that delays a falling edge based on a first input signal, a first rising edge delay circuit that delays a rising edge based on a second input signal, and a first output circuit. A second delay unit includes a second falling edge delay circuit that delays a falling edge based on the second input signal, a second rising edge delay circuit that delays a rising edge based on the first input signal, and a second output circuit.

A time measuring device comprises a signal generating circuit configured to generate a plurality of reference signals in an equivalent cycle with different phases; a first counter configured to output a fine count value, using a plurality of first pulse signals obtained from the plurality of reference signals; a second counter configured to output a coarse count value, using a plurality of second pulse signals obtained from the plurality of reference signals and having frequencies lower than frequencies of the plurality of first pulse signals; and a control unit configured to determine whether to correct the coarse count value in accordance with the fine count value and the coarse count value latched with a latch signal, and, if the coarse count value needs to be corrected, configured to calculate a bin number, using the fine count value and a coarse correction value obtained by correcting the coarse count value.

A time measuring device comprises a signal generating circuit configured to generate a plurality of reference signals in an equivalent cycle with different phases; a first counter configured to output a fine count value, using a plurality of first pulse signals obtained from the plurality of reference signals; a second counter configured to output a coarse count value, using a plurality of second pulse signals obtained from the plurality of reference signals and having frequencies lower than frequencies of the plurality of first pulse signals; and a control unit configured to determine whether to correct the coarse count value in accordance with the fine count value and the coarse count value latched with a latch signal, and, if the coarse count value needs to be corrected, configured to calculate a bin number, using the fine count value and a coarse correction value obtained by correcting the coarse count value.

A circuit includes a period calculator and a pulse width calculator. The period calculator is configured for receiving a first predetermined digital code and a second predetermined digital code, and for calculating a first calculated period value according to the first predetermined digital code, and calculating a second calculated period value according to the second predetermined digital code. The first predetermined digital code has a first predetermined period value, and the second predetermined digital code has a second predetermined period value. The pulse width calculator is configured for receiving a predetermined pulse width, and calculating a first pulse width code corresponding to the predetermined pulse width according to the first predetermined period value, the second predetermined period value, the first calculated period value, the second calculated period value and the predetermined pulse width.

A circuit includes a period calculator and a pulse width calculator. The period calculator is configured for receiving a first predetermined digital code and a second predetermined digital code, and for calculating a first calculated period value according to the first predetermined digital code, and calculating a second calculated period value according to the second predetermined digital code. The first predetermined digital code has a first predetermined period value, and the second predetermined digital code has a second predetermined period value. The pulse width calculator is configured for receiving a predetermined pulse width, and calculating a first pulse width code corresponding to the predetermined pulse width according to the first predetermined period value, the second predetermined period value, the first calculated period value, the second calculated period value and the predetermined pulse width.

There is provided a clocking device including: a clocking unit configured to count the number of clocks of a signal output from an oscillation circuit to clock a time point; a communication unit configured to receive pieces of time point information respectively from a plurality of mobile terminals; a processing unit configured to calculate a correction time of the clocking unit on the basis of time points respectively indicated by the time point information received by the communication unit and the time point clocked by the clocking unit; and a correction unit configured to correct the time point of the clocking unit on the basis of the correction time.

A reconfigurable and timely accurate method of generating, with a low latency, an output signal in response to multiple input signals, wherein said input signals occur at independent times, and wherein the occurrence of several input signals according to predetermined pattern is interpreted as a Super Event and wherein a detected Super Event triggers the production of a specific output signal heralding this Super Event, characterized in that said method comprises a first step of time acquisition of the occurrence of said input signals, a second step of adaptation of the acquisition data flow to the clock of the reconfigurable processing unit, a third step of determining the occurrence of a Super Event by comparing the events pattern to the super event definition, a fourth step identifying the Super Event and generating at least one event/signal corresponding to at least one trigger signal, a fifth step of adaptation of the generation data flow to the asynchronous generation device, a sixth step of applying a predefined delay for the issue of the at least one trigger signal, and an seventh step of outputting at least one output signal representing a trigger signal and sending it to a downstream unit.

A time measuring circuit is provided with an oscillating circuit configured to generate a low-speed clock signal and a high-speed clock signal; and a measuring circuit configured to measure target time based on clock number of the low-speed clock signal and the high-speed clock signal outputted from the oscillating circuit, wherein the low-speed clock signal has a relatively low frequency and the high-speed clock signal has a relatively high frequency. The oscillating circuit is configured to switch from outputting the low-speed clock signal to outputting the high-speed clock signal when elapsed time from when a measurement of the target time started reaches a set value, and the set value is calculated by subtracting a predetermined value from a preliminary value which is provided by a preliminary measurement measuring the target time using only the low-speed clock signal.

A time measuring circuit is provided with an oscillating circuit configured to generate a low-speed clock signal and a high-speed clock signal; and a measuring circuit configured to measure target time based on clock number of the low-speed clock signal and the high-speed clock signal outputted from the oscillating circuit, wherein the low-speed clock signal has a relatively low frequency and the high-speed clock signal has a relatively high frequency. The oscillating circuit is configured to switch from outputting the low-speed clock signal to outputting the high-speed clock signal when elapsed time from when a measurement of the target time started reaches a set value, and the set value is calculated by subtracting a predetermined value from a preliminary value which is provided by a preliminary measurement measuring the target time using only the low-speed clock signal.

A time measurement device measures a time interval between input timings of first and second pulsed target signals. The device includes: a processor; a number-of-periods detector that detects, by using a clock signal with a predetermined clock frequency and a predetermined clock period, the time interval in units of the clock period; and a phase detection unit including a band-pass filter. The band-pass filter receives at least one of the first and second target signals as a filtering target signal and extracts a signal component of the clock frequency from the filtering target signal. The phase detection unit detects a phase difference between the extracted signal and the clock signal. The processor derives, by using a result detected by the number-of-periods detector and the detected phase difference, the time interval at a resolution finer than the clock period.