An oscillating circuit includes an input terminal and an output terminal, to both of which an oscillator is coupled, a DC cut capacitor having one terminal of two terminals that is coupled to the input terminal, an inverter having an input side coupled to the other terminal of the DC cut capacitor and an output side coupled to the output terminal, a first feedback resistor coupled in parallel to the inverter, a second feedback resistor coupled in parallel to the DC cut capacitor and the inverter, and a switch coupled in parallel to the DC cut capacitor.

The invention provides a timing apparatus that can generate timing information regarding a plurality of regions without performing a complex calculation that uses software and without causing a significant increase in electric current consumption. The timing apparatus includes: a lower counter that generates a count value that indicates a time in seconds; a first group of upper counters that generates a first group of count values that indicate a time in minutes, hours, days, months and years by performing a count operation in synchronization with the count operation performed by the lower counter; and a second group of upper counters that generates a second group of count values that indicate a time in minutes, hours, days, months and years by performing a count operation in synchronization with the count operation performed by the lower counter.

The invention provides a timing apparatus that can generate timing information regarding a plurality of regions without performing a complex calculation that uses software and without causing a significant increase in electric current consumption. The timing apparatus includes: a lower counter that generates a count value that indicates a time in seconds; a first group of upper counters that generates a first group of count values that indicate a time in minutes, hours, days, months and years by performing a count operation in synchronization with the count operation performed by the lower counter; and a second group of upper counters that generates a second group of count values that indicate a time in minutes, hours, days, months and years by performing a count operation in synchronization with the count operation performed by the lower counter.

A timepiece reduces power consumption while maintaining required precision. The timepiece has a frequency divider that frequency divides an oscillation signal and outputs a reference signal; nonvolatile memory that stores information related to a temperature characteristic of the oscillation frequency of the crystal oscillator; multiple registers; a temperature measuring circuit; an evaluation circuit; and a temperature compensation circuit. The temperature compensation circuit reads the information from one of the registers and corrects the reference signal based on the read information and the temperature measurement information when the evaluation circuit determines the information stored in the multiple registers is the same; and when the evaluation circuit determines the information stored in the multiple registers is different, reads the information from the nonvolatile memory, stores the read information in the multiple registers, and corrects the reference signal based on the read information and the temperature measurement information.

A timepiece reduces power consumption while maintaining required precision. The timepiece has a frequency divider that frequency divides an oscillation signal and outputs a reference signal; nonvolatile memory that stores information related to a temperature characteristic of the oscillation frequency of the crystal oscillator; multiple registers; a temperature measuring circuit; an evaluation circuit; and a temperature compensation circuit. The temperature compensation circuit reads the information from one of the registers and corrects the reference signal based on the read information and the temperature measurement information when the evaluation circuit determines the information stored in the multiple registers is the same; and when the evaluation circuit determines the information stored in the multiple registers is different, reads the information from the nonvolatile memory, stores the read information in the multiple registers, and corrects the reference signal based on the read information and the temperature measurement information.

The present technology relates to a mobile terminal, an information processor, an information processing method, and a program capable of synchronizing time with high precision even in a case where the number of satellites that can be captured is small.

In a case where the number of satellites that can be captured is less than a predetermined number, a mobile terminal of one aspect of the present technology does not perform positioning, and generates and outputs, from a positioning unit, pulse signals at predetermined intervals synchronized with a time of the satellite that can be captured, on the basis of information from the satellite. The mobile terminal then maintains time synchronization of wireless communication with an external device of a wireless communication unit with reference to the pulse signal, and performs the wireless communication. The present technology can be applied to terminals equipped with a positioning function based on GNSS and a wireless communication function such as LPWA.

An oscillating circuit includes an input terminal and an output terminal, to both of which an oscillator is coupled, a DC cut capacitor having one terminal of two terminals that is coupled to the input terminal, an inverter having an input side coupled to the other terminal of the DC cut capacitor and an output side coupled to the output terminal, a first feedback resistor coupled in parallel to the inverter, a second feedback resistor coupled in parallel to the DC cut capacitor and the inverter, and a switch coupled in parallel to the DC cut capacitor.

An oscillating circuit includes an input terminal and an output terminal, to both of which an oscillator is coupled, a DC cut capacitor having one terminal of two terminals that is coupled to the input terminal, an inverter having an input side coupled to the other terminal of the DC cut capacitor and an output side coupled to the output terminal, a first feedback resistor coupled in parallel to the inverter, a second feedback resistor coupled in parallel to the DC cut capacitor and the inverter, and a switch coupled in parallel to the DC cut capacitor.

A current mirror arrangement for duplex bidirectional communication between two circuit units may include in each circuit unit two identical transistors with their bases (36, 37) connected together and their bases and their collectors connected to each other respectively. Further, each of the connections between the bases and the collectors may be formed via a MOSFET. The MOSFETs of both circuit units may be connected together. More specifically, the MOSFETs' parasitic diodes of each circuit unit may be arranged in opposite directions with respect to the current system. The pair of MOSFETs in a first of the two circuit units may comprise n-channel enhancement-mode MOSFETs, and the pair of MOSFETs in a second of the two circuit units may comprise p-channel enhancement-mode MOSFETs.

The method for test the rate of an electronic watch with a time base device (1) comprises three main steps for the test on test equipment. The time base device comprises at least one watch module (2) with a resonator (3) connected to an oscillator of an electronic circuit (4), which is followed by a divider circuit, which is controlled by an inhibition circuit, and which provides a divided timing signal for a motor. In a first step, a measurement is made of the frequency of the oscillator reference signal in at least one measurement period without inhibition. A second step is provided for acquiring the current inhibition value to inhibit a certain number of clock pulses in a subsequently inhibition period and to determine the inhibition value. Finally, a third step is provided for calculating the corresponding rate frequency of the watch.