To provide a low-pass filter circuit which is high in noise elimination capability and starts its output stably and at high speed, and a power supply device. A low-pass filter circuit is provided which is equipped with a capacitance element connected to an output terminal, and a resistance circuit connected between an input terminal and the output terminal, and in which the resistance circuit is equipped with a first MOS transistor connected between the input terminal and the output terminal, and an amplifier which has a first input terminal to which the input terminal is connected, a second input terminal to which the output terminal is connected, and an output terminal to which a gate of the first MOS transistor is connected, and which controls a time constant of the low-pass filter circuit.

To provide a low-pass filter circuit which is high in noise elimination capability and starts its output stably and at high speed, and a power supply device. A low-pass filter circuit is provided which is equipped with a capacitance element connected to an output terminal, and a resistance circuit connected between an input terminal and the output terminal, and in which the resistance circuit is equipped with a first MOS transistor connected between the input terminal and the output terminal, and an amplifier which has a first input terminal to which the input terminal is connected, a second input terminal to which the output terminal is connected, and an output terminal to which a gate of the first MOS transistor is connected, and which controls a time constant of the low-pass filter circuit.

A semiconductor device may include a bandgap circuit that outputs a reference voltage. The semiconductor device may also include a startup circuit coupled to the bandgap circuit. The startup circuit may connect a voltage source to a node that corresponds to an output of the bandgap circuit in response to the bandgap circuit being initialized. The startup circuit may also disconnect the voltage source from the node in response to the reference voltage being greater than a threshold.

A semiconductor device may include a bandgap circuit that outputs a reference voltage. The semiconductor device may also include a startup circuit coupled to the bandgap circuit. The startup circuit may connect a voltage source to a node that corresponds to an output of the bandgap circuit in response to the bandgap circuit being initialized. The startup circuit may also disconnect the voltage source from the node in response to the reference voltage being greater than a threshold.

A switching element drive device that reduces a switching loss while suppressing noise with an inexpensive configuration, is provided. The switching element drive device includes a current sensor configured to measure a load current flowing through a load, a voltage sensor configured to measure an input voltage inputted from a power supply, and a control part configured to output a command value of a gate drive voltage to a gate drive voltage supply part, the gate drive voltage supply part being configured to supply the gate drive voltage for driving a switching element disposed between the power supply and the load, wherein the control part is further configured to determine the command value of the gate drive voltage based on the load current and the input voltage.

A method and apparatus for current sensing and measurement employs two cascaded MOSFET current mirrors, wherein the mirrored current leaving the first current mirror is fed to the input of the second current mirror. Each current mirror contains a high current MOSFET and a low current MOSFET, connected source-to-source and gate-to-gate. The MOSFETs are matched so that drain-to-source current flowing in the high current MOSFET is proportional to the drain-to-source current flowing in the low current MOSFET. The ratio of high current to low current for each current mirror is M, where M is 100 or less. Voltage biasing networks are employed to maintain constant drain-to-source voltages for both MOSFETs in each current mirror.

This invention is an electronic circuit with a low power retention mode. A single integrated circuit includes a circuit module and a droop switch circuit supplied by a voltage regulator. In a normal mode a PMOS source-drain channel connects the voltage regulator power to the circuit module power input or isolates them dependent upon a power switch input. In a low power mode a second PMOS connected between the first PMOS gate and output diode connects the first PMOS. This supplied the circuit module from the voltage regulator power as reduced in voltage by a diode forward bias drop. This lower voltage should be sufficient for flip-flops in the circuit module to retain their state while not guaranteeing logic operation. There may be a plurality of chain connected droop switch each powering a corresponding circuit module.

This invention is an electronic circuit with a low power retention mode. A single integrated circuit includes a circuit module and a droop switch circuit supplied by a voltage regulator. In a normal mode a PMOS source-drain channel connects the voltage regulator power to the circuit module power input or isolates them dependent upon a power switch input. In a low power mode a second PMOS connected between the first PMOS gate and output diode connects the first PMOS. This supplied the circuit module from the voltage regulator power as reduced in voltage by a diode forward bias drop. This lower voltage should be sufficient for flip-flops in the circuit module to retain their state while not guaranteeing logic operation. There may be a plurality of chain connected droop switch each powering a corresponding circuit module.

Aspects of the disclosure provide a system having a power circuit. The power circuit includes a first switch circuit having at least a first transistor and a second switch circuit having at least a second transistor. Further, the power circuit includes first interconnections configured to couple the first switch circuit to driving nodes, a source node and a drain node of the power circuit, and second interconnection configured to couple the second switch circuit in parallel to the first switch circuit to the driving nodes, the source node and the drain node of the power circuit. A polarity of unbalance in the first interconnections and the second interconnections dominates a polarity of current unbalance in the first switch circuit and the second switch circuit.

Aspects of the disclosure provide a system having a power circuit. The power circuit includes a first switch circuit having at least a first transistor and a second switch circuit having at least a second transistor. Further, the power circuit includes first interconnections configured to couple the first switch circuit to driving nodes, a source node and a drain node of the power circuit, and second interconnection configured to couple the second switch circuit in parallel to the first switch circuit to the driving nodes, the source node and the drain node of the power circuit. A polarity of unbalance in the first interconnections and the second interconnections dominates a polarity of current unbalance in the first switch circuit and the second switch circuit.