A binary logic circuit for approximating a mathematical function over a predefined range as a series of linear segments, each linear segment having one of a predetermined set of fixed gradients and a corresponding base value, the binary logic circuit comprising: an input for receiving an input variable in the predefined range; a plurality of logic chains each comprising: a binary multiplier adapted to perform multiplication by a respective one of the set of fixed gradients using h−1 binary adders, where h is the extended Hamming weight; and a binary adder adapted to add a base value to the input or output of the binary multiplier; and selection logic configured to select one of the logic chains in dependence on the input variable so as to provide, for the received input variable, an approximate value of the mathematical function.

According to an embodiment, a computing apparatus includes a memory, and a processor. The memory stores N first vectors in a d-dimensional binary vector space consisting of binary values. The processor acquires a second vector in the d-dimensional binary vector space. The processor extracts M first vectors having a distance from the second vector satisfying a first condition out of the N first vectors, and calculate a distribution of distances of the M first vectors from the second vector. The processor acquires a first kernel function per a first distance between the M first vectors and the second vector in a first range. The processor generates a second kernel function based on the distribution and the first kernel functions. The processor calculates an occurrence probability of the second vector in the N first vectors based on the second kernel function.

A SAT filter builder and method for building a SAT filter is provided. Hash functions are utilized to map elements of a domain subset to a set of literals which are in turn used to create a set of equations. These equations are conjoined to provide a satisfiability instance. The satisfiability instance is provided to an equation solver and the solution is provided to an array to build the filter. A query tool is also provided which allows the filter built by the SAT filter to test an element for set membership. The query tool utilizes the same hash functions used by the SAT filter builder to map the element to be tested to a set of literals. These literals are used to create an equation. The solution identified by the SAT builder tool is then provided to the equation created by the query tool and set membership is determined by determining whether the equation provided by the query tool is satisfied by the solution provided by the SAT filter builder.

A SAT filter builder and method for building a SAT filter is provided. Hash functions are utilized to map elements of a domain subset to a set of literals which are in turn used to create a set of equations. These equations are conjoined to provide a satisfiability instance. The satisfiability instance is provided to an equation solver and the solution is provided to an array to build the filter. A query tool is also provided which allows the filter built by the SAT filter to test an element for set membership. The query tool utilizes the same hash functions used by the SAT filter builder to map the element to be tested to a set of literals. These literals are used to create an equation. The solution identified by the SAT builder tool is then provided to the equation created by the query tool and set membership is determined by determining whether the equation provided by the query tool is satisfied by the solution provided by the SAT filter builder.

Method and apparatus for performing a shift and XOR operation. In one embodiment, an apparatus includes execution resources to execute a first instruction. In response to the first instruction, said execution resources perform a shift and XOR on at least one value.

An agile frequency synthesizer with dynamic phase and pulse-width control is disclosed. In one aspect, the frequency synthesizer includes a count circuit configured to modify a stored count value by an adjustment value. The frequency synthesizer also includes an output clock generator configured to generate an output clock signal having rising and falling edges that are based at least in part on the stored count value satisfying a count threshold. The count circuit is further configured to alter at least one of the period or phase of the output clock signal based at least in part on modifying an adjustment rate of the count circuit.

Methods and systems for decimating a waveform are disclosed. The method includes dividing the waveform into a plurality of sections and performing a second order derivative operation on the sections and determining corresponding derivative values. The method further includes classifying the section as a linear region if the derivative value is within a threshold range and classifying the section as a non-linear region if the derivative value is outside the threshold range. The method also includes decimating data points of the linear regions using a coarse decimation to generate coarsely decimated data points and decimating data points of the non-linear regions using a fine decimation to generate finely decimated data points. The method also includes reconstructing a waveform using the coarsely and finely decimated data points.

Systems and methods are provided for routing quantum signals in a quantum computing system. An exemplary method includes providing a waveguide configured to be coupled to at least two modules and a nonlinear element, the waveguide configured to facilitate exchange of quantum information between the at least two modules, the waveguide having at least two waveguide modes, each waveguide mode having a respective frequency; providing a first module couplable to the waveguide at a first module frequency corresponding to a first waveguide mode and a second module couplable to the waveguide at a second mode frequency corresponding to a second waveguide mode; and driving the waveguide via the nonlinear element at a difference frequency equal to a difference between the first module frequency and the second module frequency, thereby causing exchange of quantum information between the first and the second modules.

Techniques facilitating simplified quantum programming are provided. In one example, a computer-implemented method comprises reducing, by a device operatively coupled to a processor, a first computing problem of a problem type to a second computing problem of the problem type, wherein the second computing problem is associated with a quantum circuit; facilitating, by the device, execution of the quantum circuit at a quantum computer, resulting in a first output corresponding to the second computing problem; and mapping, by the device, the first output to a second output corresponding to the first computing problem.

Provided are, among other things, systems, apparatuses methods and techniques for generating discrete-time sinusoidal sequences. One such apparatus includes a plurality of parallel processing branches, with each of the parallel processing branches operating at a subsampled rate and utilizing a recursive filter to generate sub-rate samples which represent a different subsampling phase of a complete signal that is output by the apparatus.