A direct digital synthesizer (DDS) circuit. The circuit includes a first input to receive a first fixed frequency clock signal having a first frequency, a second input to receive a second fixed frequency clock signal having a second frequency lower than the first frequency, and an output to provide an output frequency that is based at least in part on a frequency control word (FCW). The DDS circuit may include a frequency correction circuit having a first input to receive the first clock signal, a second input to receive the second clock signal, and a third input to receive the FCW, and an output to provide a frequency error of the first clock signal, the frequency error determined using the second clock signal and FCW. Alternatively, or in addition to, the DDS circuit may include an all-digital phase lock loop to correct for frequency wander of the first clock signal.

An apparatus includes a digitally controlled oscillator (DCO), which includes an inductor coupled in series with a first capacitor. The DCO further includes a second capacitor coupled in parallel with the series-coupled inductor and first capacitor, a first inverter coupled in parallel with the second capacitor, and a second inverter coupled back-to-back to the first inverter. The DCO further includes a digital-to-analog-converter (DAC) to vary a capacitance of the first capacitor.

Disclosed is a method of generating electrical signal waveforms by a generator. The generator includes a processor and a memory in communication with the processor. The memory defines a first and second table. The processor retrieves information from the first table defined in the memory, where the information is associated with a first wave shape of a first electrical signal waveform for performing a surgical procedure. The processor retrieves information from the second table defined in the memory, where the information is associated with a second wave shape of a second electrical signal waveform for performing a surgical procedure. The processor combines the first and second wave shapes to create a combined wave shape of an electrical signal waveform for performing a surgical procedure and the combined wave shape electrical signal waveform for performing a surgical procedure is delivered to a surgical instrument.

An apparatus includes a digitally controlled oscillator (DCO), which includes an inductor coupled in series with a first capacitor. The DCO further includes a second capacitor coupled in parallel with the series-coupled inductor and first capacitor, a first inverter coupled in parallel with the second capacitor, and a second inverter coupled back-to-back to the first inverter. The DCO further includes a digital-to-analog-converter (DAC) to vary a capacitance of the first capacitor.

An apparatus includes a digitally controlled oscillator (DCO), which includes an inductor coupled in series with a first capacitor. The DCO further includes a second capacitor coupled in parallel with the series-coupled inductor and first capacitor, a first inverter coupled in parallel with the second capacitor, and a second inverter coupled back-to-back to the first inverter. The DCO further includes a digital-to-analog-converter (DAC) to vary a capacitance of the first capacitor.

A test and measurement instrument for generating an analog waveform, including an interpolator configured to receive a digital signal and output interpolated samples of the digital signal at a sample rate, a filter modulation controller configured to output first filter coefficients at a first time and second filter coefficients at a second time, a convolver configured to generate a convolved signal by convolving the interpolated samples of the digital signal and the first filter coefficients and convolving the interpolated samples of the digital signal and the second filter coefficients; and a digital-to-analog converter configured to convert the convolved signal to an analog signal based on a fixed, constant clock signal.

Signal processing devices and methods estimate transforms between signals using a least squares technique. From a seed set of transform candidates, a direct least squares method applies a seed transform candidate to a reference signal and then measures correlation between the transformed reference signal and a suspect signal. For each candidate, update coordinates of reference signal features are identified in the suspect signal and provided as input to a least squares method to compute an update to the transform candidate. The method iterates so long as the update of the transform provides a better correlation. At the end of the process, the method identifies a transform or set of top transforms based on a further analysis of correlation, as well as other results.

Signal processing devices and methods estimate transforms between signals using a least squares technique. From a seed set of transform candidates, a direct least squares method applies a seed transform candidate to a reference signal and then measures correlation between the transformed reference signal and a suspect signal. For each candidate, update coordinates of reference signal features are identified in the suspect signal and provided as input to a least squares method to compute an update to the transform candidate. The method iterates so long as the update of the transform provides a better correlation. At the end of the process, the method identifies a transform or set of top transforms based on a further analysis of correlation, as well as other results.

Systems, methods, and devices for isolating a misbehaving accelerator circuit, such as an accelerator function unit or an accelerated function context, are provided. An integrated circuit may include a region that includes an accelerator circuit. When the accelerator circuit issues a request, another region of the integrated circuit or a processor connected to the integrated circuit may determine whether there is a misbehavior associated with the request and, in response to determining that there is a misbehavior associated with the request, may perform a misbehavior response to mitigate a negative impact of the misbehavior of the accelerator circuit.

A quantum processing system may include one or more superconducting qubits and a qubit controller for controlling the one or more qubits. The qubit controller includes a radio frequency generation unit comprising electronic components, which are altogether configured to generate modulated RF signals. The controller also includes a phase locked loop unit maintaining a reference clock for two or more of the components of the RF generation unit, and a timing controller including an absolute timing register, the latter accessed by the reference clock, in operation. The qubit controller comprises a sequencer coupled to the timing controller to synchronize said two or more of said components by maintaining a coherent signal for said two or more of said components, the coherent signal phase matched to the one or more qubits, to drive and/or read out the one or more qubits via modulated signals generated by the synchronized components, in operation.