In a real-time system having first and second processor systems, cooperative dynamic clock and voltage scaling (“DCVS”) may include a first processor system monitoring a condition indicative of first processor workload, adjusting a first processor operating frequency in response to a detected amount of change in the first processor workload, and providing an indication based on the detected amount of change in the first processor workload to the second processor contemporaneously with providing first processor output data to the second processor. The cooperative DCVS may further include the second processor system adjusting a second processor operating frequency in response to the indication.

In a real-time system having first and second processor systems, cooperative dynamic clock and voltage scaling (“DCVS”) may include a first processor system monitoring a condition indicative of first processor workload, adjusting a first processor operating frequency in response to a detected amount of change in the first processor workload, and providing an indication based on the detected amount of change in the first processor workload to the second processor contemporaneously with providing first processor output data to the second processor. The cooperative DCVS may further include the second processor system adjusting a second processor operating frequency in response to the indication.

A security device includes a bus interface and circuitry. The bus interface is coupled to a bus connecting between a host device and a peripheral device. The circuitry is configured to receive, via the bus interface, a clock signal of the bus, and to produce a delayed clock signal relative to the clock signal. The circuitry is further configured to monitor, using the clock signal, transactions communicated between the host device and the peripheral device, in response to identifying a given transaction, of which a portion is expected to be delayed by a predefined time delay relative to the clock signal, to sample the portion of the given transaction using the delayed clock signal, and in response to identifying, based on the sampled portion, that the given transaction violates a security policy, to apply a security action.

A security device includes a bus interface and circuitry. The bus interface is coupled to a bus connecting between a host device and a peripheral device. The circuitry is configured to receive, via the bus interface, a clock signal of the bus, and to produce a delayed clock signal relative to the clock signal. The circuitry is further configured to monitor, using the clock signal, transactions communicated between the host device and the peripheral device, in response to identifying a given transaction, of which a portion is expected to be delayed by a predefined time delay relative to the clock signal, to sample the portion of the given transaction using the delayed clock signal, and in response to identifying, based on the sampled portion, that the given transaction violates a security policy, to apply a security action.

Provided herein may be an error correction decoder, an error correction circuit having the error correction decoder, and a method of operating the error correction decoder. The error correction decoder may include a calculator configured to output an error correction message by performing an iterative decoding operation on a first codeword, a syndrome generator configured to generate a syndrome by calculating the error correction message and a parity check matrix and to output a number of iterations representing the number of times the iterative decoding operation has been performed, and an unsatisfied check node (UCN) value representing the number of unsatisfied check nodes in the syndrome, and a speed selector configured to output a speed code for controlling a speed of the iterative decoding operation depending on the number of iterations and the UCN value.

Provided herein may be an error correction decoder, an error correction circuit having the error correction decoder, and a method of operating the error correction decoder. The error correction decoder may include a calculator configured to output an error correction message by performing an iterative decoding operation on a first codeword, a syndrome generator configured to generate a syndrome by calculating the error correction message and a parity check matrix and to output a number of iterations representing the number of times the iterative decoding operation has been performed, and an unsatisfied check node (UCN) value representing the number of unsatisfied check nodes in the syndrome, and a speed selector configured to output a speed code for controlling a speed of the iterative decoding operation depending on the number of iterations and the UCN value.

The present technology pertains to a organization directory hosted by a synchronized content management system. The corporate directory can provide access to user accounts for all members of the organization to all content items in the organization directory on the respective file systems of the members' client devices. Members can reach any content item at the same path as other members relative to the organization directory root on their respective client device. In some embodiments novel access permissions are granted to maintain path consistency.

The present technology pertains to a organization directory hosted by a synchronized content management system. The corporate directory can provide access to user accounts for all members of the organization to all content items in the organization directory on the respective file systems of the members' client devices. Members can reach any content item at the same path as other members relative to the organization directory root on their respective client device. In some embodiments novel access permissions are granted to maintain path consistency.

A data processing system having high reliability and an operation method thereof are provided. The data processing system includes an arithmetic processing device including a nonvolatile memory and/or a nonvolatile register, and a monitoring system for monitoring an operation state of the arithmetic processing device. The monitoring system is a system utilizing artificial intelligence, and has a function of estimating from a program operating on the arithmetic processing device how much and which location of the arithmetic processing device will increase in temperature when the program operates. When the monitoring system estimates that the temperature of part of the arithmetic processing device will exceed a threshold value when the program operates, the monitoring system transmits an instruction to lower a clock frequency of the part of the arithmetic processing device, reduce a power supply potential of the part, or interrupt power supply to the part.

A data processing system having high reliability and an operation method thereof are provided. The data processing system includes an arithmetic processing device including a nonvolatile memory and/or a nonvolatile register, and a monitoring system for monitoring an operation state of the arithmetic processing device. The monitoring system is a system utilizing artificial intelligence, and has a function of estimating from a program operating on the arithmetic processing device how much and which location of the arithmetic processing device will increase in temperature when the program operates. When the monitoring system estimates that the temperature of part of the arithmetic processing device will exceed a threshold value when the program operates, the monitoring system transmits an instruction to lower a clock frequency of the part of the arithmetic processing device, reduce a power supply potential of the part, or interrupt power supply to the part.