A clock generator includes an input coupled to receive an input clock signal from a first clock source, and a noise rejection circuit configured to provide an output clock signal based on the input clock signal. The noise rejection circuit includes an event generator having a digital counter circuit. The event generator is configured to generate a first event signal based on a count value of the digital counter circuit, in which the noise rejection circuit is configured to produce an edge on the output clock signal in response to both the event signal and a state of the input clock signal.

A clock generator includes an input coupled to receive an input clock signal from a first clock source, and a noise rejection circuit configured to provide an output clock signal based on the input clock signal. The noise rejection circuit includes an event generator having a digital counter circuit. The event generator is configured to generate a first event signal based on a count value of the digital counter circuit, in which the noise rejection circuit is configured to produce an edge on the output clock signal in response to both the event signal and a state of the input clock signal.

An improved system for monitoring clock duty cycles, comprising: a first monitoring circuit configured to record a first quantity of high levels of the monitored clock signal sampled by a first random clock signal; a second monitoring circuit configured to record a second quantity of high levels of the monitored clock signal sampled by a second random clock signal, wherein the phase of the second random clock is adjusted by a second adjustment degree based on a first clock; a third monitoring circuit configured to record a third quantity of high levels of the monitored clock signal sampled by a third random clock signal, wherein the phase of the third random clock is the reverse of that of the first random clock; and a calculation module configured to determine a duty cycle of the monitored clock based on the first quantity, the second quantity, and the third quantity.

A relaxation oscillator includes a resistor-capacitor (RC) circuit, an integration capacitor, a sampling circuit, and a controllable oscillator. The RC circuit performs an RC charging operation to set a first voltage, performs an RC discharging operation to set a second voltage, and performs a reset operation to reset the first voltage to a first reference voltage and reset the second voltage to a second reference voltage. The sampling circuit performs a charge delivery operation to sample a voltage difference between the first voltage and the second voltage, and transfers the voltage difference to the integration capacitor. The controllable oscillator generates an output clock in response to a control input provided by the integration capacitor.

A relaxation oscillator includes a resistor-capacitor (RC) circuit, an integration capacitor, a sampling circuit, and a controllable oscillator. The RC circuit performs an RC charging operation to set a first voltage, performs an RC discharging operation to set a second voltage, and performs a reset operation to reset the first voltage to a first reference voltage and reset the second voltage to a second reference voltage. The sampling circuit performs a charge delivery operation to sample a voltage difference between the first voltage and the second voltage, and transfers the voltage difference to the integration capacitor. The controllable oscillator generates an output clock in response to a control input provided by the integration capacitor.

A signal detection circuit is provided, and includes an input switch circuit, an amplitude detection circuit, a clock generating circuit, and an integration circuit. The input switch circuit receives a reference voltage and an input voltage and selectively outputs the reference voltage or the input voltage. The amplitude detection circuit detects an output of the input switch circuit to generate an amplitude voltage. The clock generating circuit controls the input switch circuit to alternately enter first and second phases, the input switch circuit is controlled to output the reference voltage in the first phase, and output the input voltage in the second phase. The integration circuit receives the amplitude voltage as an input, and generates an integration voltage corresponding to an accumulation result within a predetermined time interval. The predetermined time interval includes at least one period that cycles between the first phase and the second phase.

A signal detection circuit is provided, and includes an input switch circuit, an amplitude detection circuit, a clock generating circuit, and an integration circuit. The input switch circuit receives a reference voltage and an input voltage and selectively outputs the reference voltage or the input voltage. The amplitude detection circuit detects an output of the input switch circuit to generate an amplitude voltage. The clock generating circuit controls the input switch circuit to alternately enter first and second phases, the input switch circuit is controlled to output the reference voltage in the first phase, and output the input voltage in the second phase. The integration circuit receives the amplitude voltage as an input, and generates an integration voltage corresponding to an accumulation result within a predetermined time interval. The predetermined time interval includes at least one period that cycles between the first phase and the second phase.

A sensor-data processing device, including at least one interface to communicate with at least one sensor element for detecting sensor events; at least one interface to communicate with at least one external computer device for processing sensor data representing the sensor events; devices for generating at least one time base specific to the sensor-data processing device; a device for assigning time stamps to the sensor events, the time stamps being based on the time base of the sensor-data processing device and being specific to the sensor-data processing device; a device for receiving a request signal from the computer device; with the aid of the computer device, the request signal being able to be assigned a time stamp based on a time base specific to the computer device; and a device for assigning a time stamp specific to the sensor-data processing device, to the request signal.

A sensor-data processing device, including at least one interface to communicate with at least one sensor element for detecting sensor events; at least one interface to communicate with at least one external computer device for processing sensor data representing the sensor events; devices for generating at least one time base specific to the sensor-data processing device; a device for assigning time stamps to the sensor events, the time stamps being based on the time base of the sensor-data processing device and being specific to the sensor-data processing device; a device for receiving a request signal from the computer device; with the aid of the computer device, the request signal being able to be assigned a time stamp based on a time base specific to the computer device; and a device for assigning a time stamp specific to the sensor-data processing device, to the request signal.

In some embodiments, a system for synchronizing content with client devices receives a request from a client device to synchronize operations pertaining to content items associated with a user account registered at the system. The request can include the operations and a cursor identifying a current position of the client in a journal of revisions on the system. Based on the operations, the system generates linearized operations associated with the content items. The linearized operations can include a respective operation derived for each of the content items from one or more of the operations. The system converts each respective operation in the linearized operations to a respective revision for the journal of revisions and, based on the cursor, determines whether the respective revision conflicts with revisions in the journal. When the respective revision does not conflict with revisions in the journal, the system adds the respective revision to the journal.