An outdoor device reset system includes a voltage regulation apparatus coupled to a power supply apparatus and an outdoor device coupled to the voltage regulation apparatus. The voltage regulation apparatus is configured to regulate a working voltage input to the outdoor device based on a feedback signal, a supply voltage from the power supply apparatus for the voltage regulation apparatus, and a reference voltage of the voltage regulation apparatus. The outdoor device is configured to determine a change amount of the working voltage, and perform a reset operation when the change amount is within a preset range.

An outdoor device reset system includes a voltage regulation apparatus coupled to a power supply apparatus and an outdoor device coupled to the voltage regulation apparatus. The voltage regulation apparatus is configured to regulate a working voltage input to the outdoor device based on a feedback signal, a supply voltage from the power supply apparatus for the voltage regulation apparatus, and a reference voltage of the voltage regulation apparatus. The outdoor device is configured to determine a change amount of the working voltage, and perform a reset operation when the change amount is within a preset range.

An example memory subsystem includes a memory component and a processing device, operatively coupled to the memory component. The processing device is configured to receive a plurality of logical-to-physical (L2P) records, wherein an L2P record of the plurality of L2P records maps a logical block address to a physical address of a memory block on the memory component; determine a sequential assist value specifying a number of logical block addresses that are mapped to consecutive physical addresses sequentially following the physical address specified by the L2P record; generate a security token encoding the sequential assist value; and associate the security token with the L2P record.

An example memory subsystem includes a memory component and a processing device, operatively coupled to the memory component. The processing device is configured to receive a plurality of logical-to-physical (L2P) records, wherein an L2P record of the plurality of L2P records maps a logical block address to a physical address of a memory block on the memory component; determine a sequential assist value specifying a number of logical block addresses that are mapped to consecutive physical addresses sequentially following the physical address specified by the L2P record; generate a security token encoding the sequential assist value; and associate the security token with the L2P record.

A microcontroller includes an input pin and internal pull-up and pull-down circuits. External pull-up and pull-down circuits are also coupled to the input pin. The microcontroller is operable according to different configuration modes which include configuring the input pin in a floating state. A control logic then configures the internal pull-up and pull-down circuits according to an internal pull-up mode to acquire a first input voltage signal (at a first logic value) from the input pin, and further configure the internal pull-up and pull-down circuits according to an internal pull-down mode to acquire a second input voltage signal (at a second logic value) from the input pin. A selection of the operating mode of the MCU is then made based on the acquired first and second logic values.

A data fabric routes requests between the plurality of requestors. A probe filter tracks the state of cached lines of memory at a probe filter coupled to the data fabric. Responsive to the data fabric leaving a non-operational power state while all requestors that are probe filter clients are in a non-operational power state, the power management controller delays a probe filter initialization state in which data regarding cached lines is initialized following the non-operational power state.

A power supply control unit controls supply and stoppage of power to a plurality of blocks having two or more modules. A clock control unit controls supply and stoppage of clocks to the two or more modules in the plurality of blocks. A first control unit verifies validity of a program stored in a storage unit. A second control unit executes the program determined to be valid as a result of verification by the first control unit. While the program is verified by the first control unit, the power supply control unit supplies power to a block including a module required for the verification, and the clock control unit stops a clock to a module not required for the verification of the block including a module required for the verification.

A method may including obtaining, for an application, an application dependency including called components, and obtaining, using the called components, a component compatibility graph including a set of nodes and a set of edges each connecting a pair of nodes in the set of nodes. The pair of nodes may include a calling node and a called node. Each node may correspond to a component. The method may further include generating, from the component compatibility graph, a set of constraints including a set of edge variables corresponding to the set of edges, selecting, using the set of constraints, an edge subset of the set of edges, and recommending, for the application, an upgrade solution including installing a called component corresponding to a called node connected by an edge in the edge subset.

A signal receiving circuit receives a reset configuration signal from an exceptional timing sequence device in a functional module and outputs a trigger signal. A first signal generation circuit generates an idle signal based at least in part on the trigger signal. The idle signal is used to configure a shutdown signal which in turn is used to shut down a first clock signal of the exceptional timing sequence device and a second clock signal in a same clock domain as the first clock signal. A second signal generation circuit generates a reset enable signal based at least in part on the trigger signal. An operational circuit performs an operation based at least in part on the reset enable signal and generates a module-based reset signal based at least in part on an operation result. The module-based reset signal is used to reset the exceptional timing sequence device in the functional module.

A signal receiving circuit receives a reset configuration signal from an exceptional timing sequence device in a functional module and outputs a trigger signal. A first signal generation circuit generates an idle signal based at least in part on the trigger signal. The idle signal is used to configure a shutdown signal which in turn is used to shut down a first clock signal of the exceptional timing sequence device and a second clock signal in a same clock domain as the first clock signal. A second signal generation circuit generates a reset enable signal based at least in part on the trigger signal. An operational circuit performs an operation based at least in part on the reset enable signal and generates a module-based reset signal based at least in part on an operation result. The module-based reset signal is used to reset the exceptional timing sequence device in the functional module.