A system which identifies a memory device using a physical unclonable function. The system performs raw read operations on every page of a block; sorts the pages into low and high groups using an average number of ones based on the raw read operations; generates unordered page pairs by sequentially selecting a first page from the low group and a second page from the high group; generates ordered page pairs by selectively converting an order of pages in each pair of the unordered page pairs; and generates a sequence for identifying the selected block based on comparing the average number of ones for pages in each ordered page pair.

An apparatus comprises at least one processing device configured to identify a snapshot lineage comprising snapshots of a storage volume, the snapshot lineage comprising (i) a local snapshot lineage stored on a storage system and (ii) cloud snapshot lineages stored on cloud storage external to the storage system, to select at least one snapshot that is to be copied from the local snapshot lineage, to determine at least two of the cloud snapshot lineages as destinations for the selected snapshot, to generate a snapshot copy job for copying the selected snapshot to the at least two cloud snapshot lineages, and to process the snapshot copy job by reading data of the selected snapshot stored in the local snapshot lineage once and writing the data of the selected snapshot to the at least two cloud snapshot lineages.

In various examples, a VPU and associated components may be optimized to improve VPU performance and throughput. For example, the VPU may include a min/max collector, automatic store predication functionality, a SIMD data path organization that allows for inter-lane sharing, a transposed load/store with stride parameter functionality, a load with permute and zero insertion functionality, hardware, logic, and memory layout functionality to allow for two point and two by two point lookups, and per memory bank load caching capabilities. In addition, decoupled accelerators may be used to offload VPU processing tasks to increase throughput and performance, and a hardware sequencer may be included in a DMA system to reduce programming complexity of the VPU and the DMA system. The DMA and VPU may execute a VPU configuration mode that allows the VPU and DMA to operate without a processing controller for performing dynamic region based data movement operations.

A computer-implemented method according to one embodiment includes causing a plurality of I/O queues to be created between an initiator and a storage target device. The created I/O queues are reserved for I/O requests for which adjustments of current priorities of extents of data associated with the I/O requests are to be performed. The method further includes determining identifying information of an I/O request sent from the initiator to the storage target device and determining whether the I/O request was sent from the initiator to the storage target device using one of the created I/O queues. In response to a determination that the I/O request was sent using a first of the created I/O queues having one of the adjustments associated therewith, a tiering manager of the storage target device is instructed to perform the adjustment on the current priority of the extent of data associated with the I/O request.

Methods, systems, and devices for adjusting a granularity associated with read disturb tracking are described. In some examples, a memory system may receive a set of read commands from a host system instructing the memory system to read data stored at a memory array. The memory system may track a quantity of executed read commands corresponding to a first portion of the memory array according to a first granularity and determine whether the quantity of read commands satisfies a threshold. If the quantity of read commands satisfies the threshold, the memory system may adjust the granularity for tracking executed read commands for the first portion from the first granularity to a second granularity. For example, the memory system may increase or decrease the granularity for tracking executed read commands for the first portion. The memory system may use the tracked quantities of executed read commands for read disturb remediation.

Methods, systems, and devices for logic remapping techniques are described. A memory system may receive a write command to store information at a first logical address of the memory system. The memory system may generate a first entry of a logical-to-physical mapping that maps the first logical address with a first physical address that stores the information. The memory system may perform a defragmentation operation or other remapping operation. In such a defragmentation operation, the memory system may remap the first logical address to a second logical address, such that the second logical address is mapped to the first physical address. The memory system may generate a second entry of a logical-to-logical mapping that maps the first logical address with the second logical address.

A method for computational storage may include storing, at a storage device, two or more portions of data, wherein a first one of the two or more portions of data comprises a first fragment of a record and a second one of the two or more portions of data comprises a second fragment of the record, and performing, by the storage device, an operation on the first and second fragments of the record. The method may further include performing, by the storage node, a second operation on first and second fragments of a second record. The operation may include a data selection operation, and the method may further include sending a result of the data selection operation to a server. The method may further include sending a result of a first data selection operation to a server.

Methods, systems, and devices for improved data management for memory are described. An apparatus may include a memory array including one or more blocks of memory cells. Data read from a block of memory cells may be written to a buffer, to support providing the data to a host system or modification of the data by the host system. If a quantity of read commands performed at the block of memory cells satisfies a threshold, the data may be written from the buffer to a different block of memory cells, rather than the block from which the data was previously read.

Methods, systems, and devices for voltage regulation distribution for stacked memory are described. A stacked memory device may support various techniques for coupling between voltage regulation circuitry of multiple memory dies, or for coupling of voltage regulation circuitry of some memory dies with circuitry associated with operating memory arrays of other memory dies. In some examples, such techniques may include cross-coupling of voltage regulation circuitry based on access activity or a degree of access activity for array circuitry. In some examples, such techniques may include isolating voltage regulation circuitry based on access activity or a degree of access activity for array circuitry. Dynamic coupling or isolation between voltage regulation circuitry may be supported by various signaling related to a stacked memory device, such as signaling between the stacked memory dies, signaling between a memory die and a central controller, or signaling between the stacked memory device and a host device.

Implementations disclosed describe methods and systems to perform the methods of optimizing a size of memory used for accumulation of neural node outputs and for supporting multiple computational paths in neural networks. In one example, a size of memory used to perform neural layer computations is reduced by performing nodal computations in multiple batches, followed by rescaling and accumulation of nodal outputs. In another example, execution of parallel branches of neural node computations include evaluating, prior to the actual execution, the amount of memory resources needed to execute a particular order of branches sequentially and select the order that minimizes this amount or keeps this amount below a target threshold.