A memory module is provided. The memory module includes: a control chip, at least one data flash memory chip, at least two memory cells, and at least one non-volatile memory, each of the at least one data flash memory chip is connected to at least one of the at least two memory cells and at least one of the at least one non-volatile memory, the control chip is connected to the at least one data flash memory chip and the at least two memory cells, and the memory is further connected to at least one capacitor; the control chip is configured to send a control command; and each of the at least one data flash memory chip is configured to perform, based on the control command from the control chip, data processing between the memory cell connected thereto and the non-volatile memory connected thereto.

A method of circuit conception of a computational memory circuit including a memory having memory cells, the method including: receiving an indication of the memory storage size and an indication of an instruction frequency of the instructions to be executed by the computational memory circuit; evaluating for a plurality of candidate types of memory cells, a number representing an average number of cycles of the memory of the computational memory circuit per instruction to be executed; determining, for each of the plurality of candidate types of memory cells, a minimum operating frequency of the computational memory circuit based on the number N and on the memory storage size; selecting one of the plurality of candidate types of memory cells based on the determined minimum operating frequency; and performing the circuit conception based on the selected type of candidate memory cell.

A memory device can sense stored data during memory read operations using a reference trim, and a memory built-in self-test system can perform a multiple step process to set the reference trim for the memory device. The memory built-in self-test system can set a reference trim range that corresponds to a range of available reference trim values and then select one of the reference trim values in the reference trim range as the reference trim for the memory device. The memory built-in self-test system can set the reference trim range by prompting performance of the memory read operations using different positions of the reference trim range relative to read characteristics of the memory device and set a position for the reference trim range relative to the read characteristics of the memory device based on failures of the memory device to correctly sense the stored data during the memory read operations.

A storage system. In some embodiments, the storage system includes a plurality of object stores, and a plurality of data managers, connected to the object stores. The plurality of data managers may include a plurality of processing circuits. A first processing circuit of the plurality of processing circuits may be configured to process primarily input-output operations, and a second processing circuit of the plurality of processing circuits may be configured to process primarily input-output completions.

Method and system for training a machine learning model based on a training dataset formed by data objects distributed across a virtual object storage service. The method comprises fetching from the virtual object storage service, the training dataset; copying the fetched training dataset on a first local storage device and maintaining a list of modifications executed on the training dataset that occurred on the virtual object storage service. The method comprises, upon receiving a request to initiate training of the machine learning model, generating a synchronized training dataset mirroring the training dataset stored in the virtual object storage service; storing the synchronized training dataset in a second local storage device; and fetching training data from the synchronized training dataset stored in the second local storage device as the training of the machine learning model is executed.

A method of storing data, a method of reading data, a device, and a storage medium are provided, which relate to a field of artificial intelligence, in particular to the fields of cloud computing technology and distributed storage technology. A specific implementation scheme includes: storing at least one target data into a target file in a storage class memory device; recording a storage address of the at least one target data in the storage class memory device in a dynamic random access memory as a first index data; and synchronously storing the first index data into the storage class memory device as a second index data.

A method for computational storage may include receiving, at a storage device, a modified version of a portion of data, generating, at the storage device, a restored portion of data from the modified version of the portion of data, and performing, at the storage device, an operation on the restored portion of data. The method may further include receiving, at the storage device, a request to perform the operation on the portion of data. The generating may include decompressing the modified version of the portion of data. The generating may include decrypting the modified version of the portion of data. The method may further include sending, from the storage device, a result of the operation on the restored portion of data. The operation may include a filtering operation. The operation may include a scanning operation. The method may further include dividing data to generate the portion of data.

In a case of performing control of migrating data from a relatively-old-generation magnetic tape as a migration-source magnetic tape included in one storage pool of the plurality of storage pools to relatively-new-generation magnetic tapes as migration-destination magnetic tapes included in each of the plurality of storage pools, an information processing apparatus excludes, from migration targets, data recorded in a relatively-new-generation magnetic tape included in a storage pool to which the migration-destination magnetic tape belongs.

Aspects of the disclosure are directed to hardware interconnects and corresponding devices and systems for non-coherently accessing data in shared memory devices. Data produced and consumed by devices implementing the hardware interconnect can read and write directly to a memory device shared by multiple devices, and limit coherent memory transactions to relatively smaller flags and descriptors used to facilitate data transmission as described herein. Devices can communicate less data on input/output channels, and more data on memory and cache channels that are more efficient for data transmission. Aspects of the disclosure are directed to devices configured to process data that is read from the shared memory device. Devices, such as hardware accelerators, can receive data indicating addresses for different data buffers with data for processing, and non-coherently read or write the contents of the data buffers on a memory device shared between the accelerators and a host device.

An device is disclosed. A first buffer to store a query data point, and a second buffer to store a matrix of candidate data points. A processing element may process the query data point and the matrix of candidate data points to identify candidate data points in the matrix of candidate data points that are nearest to the query data point.