G06F3/06

INFORMATION PROCESSING APPARATUS, INFORMATION PROCESSING METHOD, AND INFORMATION PROCESSING PROGRAM
20230051963 · 2023-02-16 ·

An information processing apparatus selects a magnetic tape as a data migration target from among a plurality of migration-source magnetic tapes based on an index value correlated with a read frequency of valid data recorded in the magnetic tape, the index value being calculated for each of the magnetic tapes, specifies valid data recorded in the selected magnetic tape, and performs control of migrating the valid data to a migration-destination magnetic tape.

RUNTIME INTEGRITY CHECKING FOR A MEMORY SYSTEM

Various embodiments relate to a memory controller, including: a memory interface connected to a memory; an address and command logic connected to the memory interface and a command interface, wherein the address and control logic is configured to receive a memory read request; a memory scrubber configured to cycle through memory locations and to read data from those locations; a region selector configured to determine when a memory location read by the memory scrubber is within an integrity checked memory region; a runtime integrity check (RTIC) engine connected to a read data path of the memory interface, wherein the RTIC engine is configured to calculate an integrity check value for the RTIC region using data read from the checked memory region by the memory scrubber; and a RTIC controller configured to compare the calculated integrity check value for the checked memory region to a reference integrity check value for the checked memory region.

SYSTEMS AND METHODS FOR NVMe OVER FABRIC (NVMe-oF) NAMESPACE-BASED ZONING

A traditional storage platform performs many basic functions, such as storage partitions allocation (i.e., namespace masking) and many advanced functions, such as deduplication or dynamic storage allocation. These functions need to be managed and this results in a multiple management system paradigm, in which a fabric management application manages the fabric connectivity policies (i.e., Zoning), while a storage management application manages the storage namespace mappings and advanced functions. Embodiments herein provide for centralized management for both connectivity and storage namespace mapping, among other advanced features. Namespace zoning information may comprise Namespace ZoneGroups, Namespace Zones, Namespace Zone Members, Namespace ZoneAlias, and Namespace ZoneAlias Members, which expand the NVMe-oF zoning framework from just connectivity control to full Namespaces allocation.

MEMORY EXPANSION WITH PERSISTENT PREDICTIVE PREFETCHING
20230052700 · 2023-02-16 ·

A memory device with non-volatile memory and persistent predictive prefetching provides highspeed storage to a computer system. The memory device uses a non-volatile memory to store data and a volatile memory to cache the data from the non-volatile memory. The computer system sends access requests to obtain data in the non-volatile memory. A prediction engine in the memory device receives the access requests. The prediction engine compute access histories based on the access requests and stores them in an access history table. The prediction engine computes prediction of non-volatile memory addresses that will be accessed in the future based on the stored access history table. The prediction engine causes to store the data from the predicted addresses of the non-volatile memory in the volatile memory. The memory device stores the prediction in the non-volatile memory so the past predictions can be used after restarting the computer system.

SYSTEM SUPPORTING VIRTUALIZATION OF SR-IOV CAPABLE DEVICES
20230051825 · 2023-02-16 ·

An apparatus supports single root input/output virtualization (SR-IOV) capable devices. The apparatus includes input/output ports, and SR-IOV capable PCIe devices. Each SR-IOV capable PCIe device has one or more namespaces or controller memory buffers. The SR-IOV capable PCIe device provides one or more physical functions and virtual functions that can access the one or more namespaces or controller memory buffers. A PCIe switch controller communicates with host servers coupled to the input/output ports, and assigns one or more virtual functions to each host device, and enables the host devices to access one or more namespaces or controller memory buffers through the assigned virtual functions. The PCIe device is configured to attach one or more namespaces or one or more partitions of one or more controller memory buffers to each virtual function, set at least one namespace or controller memory buffer to a shared state and allow different host devices to access the same namespace or controller memory buffer using respective assigned virtual functions.

REDUCING WRITE AMPLIFICATION AND OVER-PROVISIONING USING FLASH TRANSLATION LAYER SYNCHRONIZATION

A host Flash Translation Layer (FTL) synchronizes host FTL operations with the drive FTL operations to reduce write amplification and over-provisioning. Embodiments of FTL synchronization map, at the host FTL software (SW) stack level, logical bands in which data is managed, referred to as host bands, to the physical bands on a drive where data is stored. The host FTL tracks validity levels of data managed in host bands to determine validity levels of data stored in corresponding physical bands, and optimizes defragmentation operations (such as garbage collection processes and trim operations) applied by the host FTL SW stack to the physical bands based on the tracked validity levels.

USING PER MEMORY BANK LOAD CACHES FOR REDUCING POWER USE IN A SYSTEM ON A CHIP

In various examples, a VPU and associated components may be optimized to improve VPU performance and throughput. For example, the VPU may include a min/max collector, automatic store predication functionality, a SIMD data path organization that allows for inter-lane sharing, a transposed load/store with stride parameter functionality, a load with permute and zero insertion functionality, hardware, logic, and memory layout functionality to allow for two point and two by two point lookups, and per memory bank load caching capabilities. In addition, decoupled accelerators may be used to offload VPU processing tasks to increase throughput and performance, and a hardware sequencer may be included in a DMA system to reduce programming complexity of the VPU and the DMA system. The DMA and VPU may execute a VPU configuration mode that allows the VPU and DMA to operate without a processing controller for performing dynamic region based data movement operations.

STORAGE VOLUME SYNCHRONIZATIONS RESPONSIVE TO COMMUNICATION LINK RECOVERIES
20230049823 · 2023-02-16 ·

In some examples, a system detects recovery, from an unavailable state, of a communication link between a first storage system that includes a first storage volume and a second storage system that includes a second storage volume that is to be a synchronized version of the first storage volume, where while the communication link is in the unavailable state the second storage volume is in an offline state and the first storage volume is in an online state. In response to detecting the recovery of the communication link, the system sends a first tracking metadata for the first storage volume from the first storage system to the second storage system, and in response to receipt of the first tracking metadata at the second storage system that maintains a second tracking metadata for the second storage volume, the system transitions the second storage volume from the offline state to a controlled online state, and initiates a synchronization process to synchronize the second storage volume with the first storage volume.

OPERATING METHOD OF HOST DEVICE AND STORAGE DEVICE AND STORAGE DEVICE

A method of operating a host device to control a storage device which includes a register is provided. The method includes: providing the storage device with a partial array refresh setting indicating a non-masking segment among a masking segment and the non-masking segment; providing a refresh command to the storage device; and providing a write command for the masking segment to the storage device to control the storage device to store data while a partial array refresh is performed in the storage device based on the refresh command.

IMPLEMENTING MAPPING DATA STRUCTURES TO MINIMIZE SEQUENTIALLY WRITTEN DATA ACCESSES
20230048104 · 2023-02-16 ·

A system includes a memory device, and a processing device, operatively coupled to the memory device, to perform operations including receiving a request to sequentially write data to a block of a memory device, in response to receiving the request, writing the data to the block to obtain sequentially written data, initiating accumulation of logical-to-physical (L2P) mapping data corresponding to the sequentially written data, determining that a criterion for terminating the accumulation of the L2P mapping data is satisfied, in response to determining that the criterion is satisfied, terminating the accumulation of the L2P mapping data to obtain accumulated L2P mapping data, and updating an L2P mapping data structure based on the accumulated L2P mapping data.