G06F3/06

HOST, OPERATING METHOD OF HOST AND STORAGE SYSTEM

A host includes: an index tree storing an index including information for identifying a versioning key; and an index update buffer storing a write key included in data subject to a write request and the versioning key corresponding to the write key. When a preset update condition is satisfied, the host transfers the versioning key stored in the index update buffer to the index tree, and when the index update buffer requires recovery, the host designates a recovery section of memory of the storage device including data corresponding to the versioning key which has not been updated to the index tree, to be read by a plurality of threads, reads data included in the recovery section from the storage device through the plurality of threads, and inserts the read data into the index update buffer to recover the index update buffer.

DATA MIGRATION SCHEDULE PREDICTION USING MACHINE LEARNING
20230051103 · 2023-02-16 ·

Various embodiments provide for one or more processor instructions and memory instructions that enable a memory sub-system to predict a schedule for migrating data between memory devices, which can be part of a memory sub-system.

STORAGE SYSTEM AND METHOD FOR ACCESSING SAME
20230049799 · 2023-02-16 ·

A data access system including a processor and a storage system including a main memory and a cache module. The cache module includes a FLC controller and a cache. The cache is configured as a FLC to be accessed prior to accessing the main memory. The processor is coupled to levels of cache separate from the FLC. The processor generates, in response to data required by the processor not being in the levels of cache, a physical address corresponding to a physical location in the storage system. The FLC controller generates a virtual address based on the physical address. The virtual address corresponds to a physical location within the FLC or the main memory. The cache module causes, in response to the virtual address not corresponding to the physical location within the FLC, the data required by the processor to be retrieved from the main memory.

COMPLETION FLAG FOR MEMORY OPERATIONS
20230046535 · 2023-02-16 ·

Methods, systems, and devices for using a completion flag for memory operations are described. A completion flag for a memory device may indicate whether at least one access operation has been completed at the memory device. A controller may poll the completion flag, and if the completion flag indicates that at least one access operation has been completed at the memory device, the controller may poll a status register for the memory device to obtain additional information regarding one or more completed access operations at the memory device.

DYNAMIC STATUS REGISTERS ARRAY
20230046313 · 2023-02-16 ·

Methods, systems, and devices for dynamic status registers array are described. An apparatus may include one or more memory dice coupled with a data bus. The apparatus may further include a controller coupled with each of the memory dice via the data bus that is configured to transmit a first command associated with a first operation to a first memory die. The first command may assign an associated operation (e.g., the first operation) to a queue slot of a status bank that is associated with at least the first memory die. The controller may further transmit second command to the first memory die to request a status of the first operation. The controller may receive a status of the first operation via a channel (e.g., a first channel) of the data bus that is based on the assigned queue slot of the status bank.

METHOD AND SYSTEM FOR BUFFER ALLOCATION MANAGEMENT FOR A MEMORY DEVICE

Example implementations include a non-transitory processor-readable media comprising processor-readable instructions that when executed by at least one processor of a controller, causes the processor to generate at least one memory address corresponding respectively to at least one command block, the command block being associated with a command to a memory device, allocate the memory address to a buffer addressing unit associated with a host interface, the memory address including a buffer memory identifier associated with a buffer memory block and a buffer memory address associated with the buffer memory block, and update a request count associated with the buffer memory block by incrementing a reference counter associated with the buffer memory block.

SEPARATION OF LOGICAL AND PHYSICAL STORAGE IN A DISTRIBUTED DATABASE SYSTEM

Distributed database systems including compute nodes and page servers are described herein that enable separating logical and physical storage of database files in a distributed database system. A distributed database system includes a page server and a compute node and is configured to store a logical database file that includes data and is associated with a file identifier. Each page server is configurable to store slices (i.e., subportions) of the logical database file. The compute node is coupled to the plurality of page servers and configured to store the logical database file responsive to a received command. In an aspect, such storage may comprise slicing the data comprising the logical database file into a set of slices with each being associated with a respective page server, maintaining an endpoint mapping for each slice of the first set of slices, and transmitting each slice to the associated for storage thereby.

SYNCHRONIZING CONTROL OPERATIONS OF A NEAR MEMORY PROCESSING MODULE WITH A HOST SYSTEM

A Near Memory Processing (NMP) module including: a plurality of memory units: an Input/Output (I/O) interface configured to receive commands from a host system, wherein the host system includes a host memory controller configured to access the plurality of memory units: a decoder configured to decode the commands and generate a trigger; and an NMP memory controller configured to: receive the trigger from the decoder; and generate a signal in response to the trigger to synchronize the NMP module with the host system.

INFORMATION PROCESSING APPARATUS, INFORMATION PROCESSING METHOD, AND INFORMATION PROCESSING PROGRAM
20230047128 · 2023-02-16 ·

An information processing apparatus performs first migration processing of migrating data from a relatively-old-generation magnetic tape included in one storage pool of a plurality of storage pools to relatively-new-generation magnetic tapes included in each of the plurality of storage pools in a case where the number of tape drives which are available for data migration is equal to or larger than a threshold value, the tape drives being relatively-new-generation tape drives among a plurality of generations of tape drives, and performs second migration processing of migrating data from migration-source magnetic tapes as relatively-old-generation magnetic tapes included in the storage pool to migration-destination magnetic tapes of which the number is smaller than a multiplicity in a case where the number of the tape drives is smaller than the threshold value.

TECHNIQUES FOR NON-CONSECUTIVE LOGICAL ADDRESSES
20230046402 · 2023-02-16 ·

Methods, systems, and devices for memory operations are described. A first set of commands may be received for accessing a memory device. The first set of commands may include non-consecutive logical addresses that correspond to consecutively indexed physical addresses. A determination that the non-consecutive logical addresses correspond to consecutively indexed physical addresses may be determined based on a first mapping stored in a volatile memory. A second mapping may be transferred to the volatile memory based on the determination. The second mapping may include an indication of whether information stored at a set of physical address is valid. A second set of commands including non-consecutive logical addresses may be received for accessing the memory device. Data for the second set of commands that include the non-consecutive logical addresses may be retrieved from the memory device using the second mapping.