An integrated circuit includes signal-source circuitry (SSC), an SSC power supply circuit (SSC-PS) and a digitization circuit. The SSC is configured to generate an output signal, which is guaranteed to meet specified electrical parameters provided that a supply voltage to the SSC is within a specified operating voltage range. The SSC-PS is configured to power the SSC with a reduced voltage that is below the specified operating voltage range, thereby causing the output signal to be noisy. The digitization circuit is configured to digitize the noisy output signal so as to generate a respective sequence of random numbers.

A storage device and a data access method are provided. The storage device includes a primary storage unit and at least one additional unit. The primary storage unit includes: a primary memory element configured to store secret data and a primary access unit configured to receive an external access command. Each additional unit is configured to receive the external access command. Each additional unit includes: an additional memory element configured to store non-specific data, a local access generation element configured to trigger generating an internal access command based on the external access command, and an additional access unit configured to receive a local access command. The primary storage unit and each additional unit are coupled to a same power rail and a connection wire to simultaneously receive the external access command to parallelly (simultaneously) access the secret data and the non-specific data stored in each additional unit.

The presented invention relates to a method and device for the quantum generation of random numbers. The invention can be implemented in generation of random numbers in lotteries and gaming. The device for a self-testing quantum number generator especially in lotteries and gaming comprising: interferometer, a control unit CU connected to the signal source S, the signal is with interference property, components A that modify the signal's properties, and detectors D for measuring the signal's intensity by electrical wires. Components A are controlled by the control unit CU via electrical wires with parameters x. Detectors D are configured to measure signal intensity and send the measurement results d, via electrical wires to the control unit CU. The control unit CU performs a self-test based on the measurement results d and returns its outcome Hmin. The control unit CU returns random numbers d, and the result of self-test Hmin.

A carry-lookahead adder is provided. First XOR gate receives a first mask value and a second mask value to provide a variable. First mask unit performs a first mask operation on first input data with the variable to obtain first masked data. A half adder receives the first masked data and second input data to generate a propagation value and an intermediate generation value. Second mask unit performs a second mask operation on the propagation value with a third mask value to obtain second masked data. A logic circuit provides a generation value according to the propagation value, the intermediate generation value and the second mask value. A carry-lookahead generator provides a carry output and a carry value according to a carry input, the generation value and the propagation value. Second XOR gate receives the second masked data and the carry value to provide a sum output.

A random noise generator for generating a plurality of random noise samples per clock cycle, the noise samples having a distribution. The random noise generator comprises at least a first comparator unit and a second comparator unit, the first comparator unit configured to generate a first plurality of samples representing a high-probability part of the distribution and the second comparator unit configured to generate a second plurality of samples representing a low-probability part of the distribution; and a random selection unit connected to at least the first comparator unit and the second comparator unit. The random selection unit is configured to receive the first plurality of samples generated by the first comparator unit and the second plurality of samples generated by the second comparator unit, to output a random selection of samples from the first plurality of samples and the second plurality of samples.

A random noise generator for generating a plurality of random noise samples per clock cycle, the noise samples having a distribution. The random noise generator comprises at least a first comparator unit and a second comparator unit, the first comparator unit configured to generate a first plurality of samples representing a high-probability part of the distribution and the second comparator unit configured to generate a second plurality of samples representing a low-probability part of the distribution; and a random selection unit connected to at least the first comparator unit and the second comparator unit. The random selection unit is configured to receive the first plurality of samples generated by the first comparator unit and the second plurality of samples generated by the second comparator unit, to output a random selection of samples from the first plurality of samples and the second plurality of samples.

A clock signal generation circuit includes: a triangular wave generation circuit configured to generate a triangular wave signal; a pseudo-random number generation circuit configured to generate a pseudo-random number signal; a limiter circuit configured to perform a limitation process of limiting an amount of change per unit time in the pseudo-random number signal and generate the pseudo-random number signal subjected to the limitation process as a limiter signal; a linear arithmetic circuit configured to generate a frequency control signal by performing a linear arithmetic operation on the triangular wave signal and the limiter signal; and an oscillator configured to generate a clock signal having a frequency corresponding to the frequency control signal.

An integrated circuit chip includes a plurality of function blocks; a mode controller configured to convert an input signal, received from an external device through an input/output pin, into an input pattern and test mode setting data which include a plurality of bits, and to output the test mode setting data and a mode switching enable signal when a secure pattern generated therein is the same as the input pattern; and a mode setting module configured to control the plurality of function blocks to operate in a test mode according to the mode setting data, in response to the test mode switching enable signal.

An integrated circuit chip includes a plurality of function blocks; a mode controller configured to convert an input signal, received from an external device through an input/output pin, into an input pattern and test mode setting data which include a plurality of bits, and to output the test mode setting data and a mode switching enable signal when a secure pattern generated therein is the same as the input pattern; and a mode setting module configured to control the plurality of function blocks to operate in a test mode according to the mode setting data, in response to the test mode switching enable signal.

Briefly, example methods, apparatuses, and/or articles of manufacture are disclosed that may be implemented, in whole or in part, using one or more computing devices to facilitate and/or support one or more operations and/or techniques for an autonomous pseudo-random seed generator (APRSG) for embedded computing devices, which may include IoT-type devices, such as implemented in connection with one or more computing and/or communication networks and/or protocols.