In one embodiment of the present invention, a position-based dynamics (PBD) framework provides realistic modeling and simulation for elastic rods. In particular, the twisting and bending physics of elastic rods is incorporated into the PBD framework. In operation, an elastic rod model generator represents the center line of an elastic rod as a polyline of points connected via edges. For each edge, the elastic rod model generator adds a ghost point to define the orientation of a material frame that encodes the twist of the edge. Subsequently, a PBD simulator solves for positions of both points and ghost points that, together, represent the evolving position and torsion of the elastic rod. Advantageously, the ghost points enable more realistic animation of deformable objects (e.g., curly hair) than conventional PBD frameworks. Further, unlike force based methods, elastic rod simulation in the PBD framework performs acceptably in environments where speed is critical.

A semiconductor device having a novel structure is provided. The semiconductor device includes a plurality of operation circuits that can switch different kinds of operation processing; a plurality of switch circuits that can switch a connection state between the operation circuits; and a controller. The operation circuit includes a first memory that stores data corresponding to a weight parameter used in the plurality of kinds of operation processing. The operation circuit executes a product-sum operation by switching weight data in accordance with a context. The switch circuit includes a second memory that stores data for switching a plurality of connection states in response to switching of a second context signal. The controller generates a second context signal on the basis of a first context signal. The amount of data stored in the second memory can be smaller than the amount of data stored in the first memory in the operation circuit.

Introduced here is a technique to detect and/or correct errors in computation. The ability to correct errors in computation can increase the speed of the processor, reduce the power consumption of the processor, and reduce the distance between the transistors within the processor because the errors thus generated can be detected and corrected. In one embodiment, an error correcting module, running either in software or in hardware, can detect an error in matrix multiplication, by calculating an expected sum of all elements in the resulting matrix, and an actual sum of all elements in the resulting matrix. When there is a difference between the expected sum and the resulting sum, the error correcting module detects an error. In another embodiment, in addition to detecting the error, the error correcting module can determine the location and the magnitude of the error, thus correcting the erroneous computation.

Improved computer-implemented tools for use in modeling/simulating spatial charge distributions for electrophysiological systems are provided. The improvements are in three areas: (1) the use of solid angles to calculate quantities of free charge and/or bound charge in calculation cells and/or the movement of quantities of free charge across one or more faces of a calculation cell; (2) the use of flattened calculations cells having only two faces with substantial areas as seen from the free charge and/or the bound charge of the electrophysiological system; and (3) the use of at least two spatial charge distributions, specifically, at least one for bound charge and at least one for free charge, so as to include the effects of relative dielectric constants greater than 1.0 for part or all of an electrophysiological system. The three improvements can be used individually or in combinations.

A system and method which allows the basic checkpoint-reverse-mode AD strategy (of recursively decomposing the computation to reduce storage requirements of reverse-mode AD) to be applied to arbitrary programs: not just programs consisting of loops, but programs with arbitrarily complex control flow. The method comprises (a) transforming the program into a formalism that allows convenient manipulation by formal tools, and (b) introducing a set of operators to allow computations to be decomposed by running them for a given period of time then pausing them, while treating the paused program as a value subject to manipulation.

A system and method which allows the basic checkpoint-reverse-mode AD strategy (of recursively decomposing the computation to reduce storage requirements of reverse-mode AD) to be applied to arbitrary programs: not just programs consisting of loops, but programs with arbitrarily complex control flow. The method comprises (a) transforming the program into a formalism that allows convenient manipulation by formal tools, and (b) introducing a set of operators to allow computations to be decomposed by running them for a given period of time then pausing them, while treating the paused program as a value subject to manipulation.

A model assessor retrieves a plurality of predicted outputs from a plurality of models, each predicted output generated using one of the models based on one or more data inputs and a regression model. The model assessor generates a candidate model, which includes as input 1) the one or more data inputs of a selected model of the plurality of models and 2) a predictive output of one or more other models of the plurality of models or one or more other data inputs. A correlation is computed between an actual output and a predicted output of the candidate model, and the model assessor determines if the correlation score exceeds a threshold criteria. If so, the selected model is replaced with the candidate model. Otherwise, the candidate model is deleted.

An arithmetic logic unit according to an embodiment of the present technology includes: a plurality of input lines; and a multiply-accumulate operation device. Pulse signals corresponding to input values are input to the plurality of input lines. The multiply-accumulate operation device includes a plurality of multiplication units that generates, on the basis of the pulse signals input to each of the plurality of input lines, charges corresponding to multiplication values obtained by multiplying the input values by weight values, and an output unit that outputs a multiply-accumulate signal representing a sum of the multiplication values by accumulating the charges corresponding to the multiplication values generated by each of the plurality of multiplication units. A value of at least one of the input value or the weight value is limited.

A semiconductor device that updates a weight coefficient used for arithmetic operation by an artificial neural network is provided. Each of the first to third memory cells draws a current corresponding to data of its retention node and changes the data in accordance with the potentials of first and second wirings. When a weight coefficient and first and second reference data are held in the retention nodes of the first to third memory cells, the first circuit supplies, to a third wiring, a constant currents drawn by the second and third memory cells. When input data is input to the first wiring, a difference current between the constant current and a current drawn by the first memory cell is changed, and the second circuit outputs arithmetic result data corresponding to the change. The third circuit inputs update data corresponding to the arithmetic result data to the second wiring.

A semiconductor device that updates a weight coefficient used for arithmetic operation by an artificial neural network is provided. Each of the first to third memory cells draws a current corresponding to data of its retention node and changes the data in accordance with the potentials of first and second wirings. When a weight coefficient and first and second reference data are held in the retention nodes of the first to third memory cells, the first circuit supplies, to a third wiring, a constant currents drawn by the second and third memory cells. When input data is input to the first wiring, a difference current between the constant current and a current drawn by the first memory cell is changed, and the second circuit outputs arithmetic result data corresponding to the change. The third circuit inputs update data corresponding to the arithmetic result data to the second wiring.