A permutation algorithm using modular arithmetic is applied to the cells of one or more specific fields of a database or other file type. This permutation reorders the cells of the specific field(s) without altering content of any individual cell, thereby hiding relationships between cells of the permuted field(s) and the other information in the associated records. The permutation algorithm may use modular addition and modular subtraction, in either order. Different permutation algorithms may use varying numbers of parameters. To locate a specific cell in a permuted field, the parameter(s) from the permutation, an identification of the specific record associated with the cell, and an identification of the specific permuted field are applied in a modular arithmetic operation. A specific record with which a specific cell in a permuted field is associated may be obtained by an inverse modular arithmetic operation.

The embodiments of the present disclosure provide a random number generation circuit, including: a random number generator, including a feedback module and a plurality of sequentially connected flip-flops, where an output terminal of a previous flip-flop being connected to an input terminal of a next flip-flop, the output terminal of each of the flip-flops serving as an output terminal of the random number generator, and an output terminal of the feedback module being connected to the input terminal of one of the flip-flops; the feedback module being configured to receive selection signals and select, on the basis of the selection signals, the output terminals of two of the flip-flops as input terminals of the feedback module; and the random number generator being configured to output a plurality of first random numbers corresponding to corresponding selection signals in each counting cycle.

The embodiments of the present disclosure provide a random number generation circuit, including: a random number generator, including a feedback module and a plurality of sequentially connected flip-flops, where an output terminal of a previous flip-flop being connected to an input terminal of a next flip-flop, the output terminal of each of the flip-flops serving as an output terminal of the random number generator, and an output terminal of the feedback module being connected to the input terminal of one of the flip-flops; the feedback module being configured to receive selection signals and select, on the basis of the selection signals, the output terminals of two of the flip-flops as input terminals of the feedback module; and the random number generator being configured to output a plurality of first random numbers corresponding to corresponding selection signals in each counting cycle.

Embodiments of the present disclosure provide a random number generator circuit, including: a random number generator, configured to output a plurality of first random numbers in each counting cycle; a control signal generation module, configured to receive a trigger signal and output control signals corresponding to different first random numbers based on the trigger signal; and a multi-select module, configured to receive the first random number and the control signal corresponding to the first random number, based on the control signal to adjust at least one bit position of the first random number, obtain a second random number, and output a plurality of the second random numbers.

Embodiments of the present disclosure provide a random number generator circuit, including: a random number generator, configured to output a plurality of first random numbers in each counting cycle; a control signal generation module, configured to receive a trigger signal and output control signals corresponding to different first random numbers based on the trigger signal; and a multi-select module, configured to receive the first random number and the control signal corresponding to the first random number, based on the control signal to adjust at least one bit position of the first random number, obtain a second random number, and output a plurality of the second random numbers.

The present disclosure relates to a converter for data type conversion, a method for data type conversion, an integrated circuit chip, and a calculation apparatus, where the calculation apparatus may be included in a combined processing apparatus, where the combined processing apparatus may further include a general interconnection interface and other processing apparatus. The calculation apparatus interacts with other processing apparatus to jointly complete calculation operations specified by users. The combined processing apparatus may further include a storage apparatus. The storage apparatus is respectively connected to the calculation apparatus and other processing apparatus, and the storage apparatus is used for storing data of the calculation apparatus and other processing apparatus. A solution of the present disclosure may be widely applied to various data type conversion applications.

The present disclosure relates to a converter for data type conversion, a method for data type conversion, an integrated circuit chip, and a calculation apparatus, where the calculation apparatus may be included in a combined processing apparatus, where the combined processing apparatus may further include a general interconnection interface and other processing apparatus. The calculation apparatus interacts with other processing apparatus to jointly complete calculation operations specified by users. The combined processing apparatus may further include a storage apparatus. The storage apparatus is respectively connected to the calculation apparatus and other processing apparatus, and the storage apparatus is used for storing data of the calculation apparatus and other processing apparatus. A solution of the present disclosure may be widely applied to various data type conversion applications.

A device includes a memory, which, in operation, stores one or more look-up tables, and cryptographic circuitry coupled to the memory. The cryptographic circuitry, in operation, multiplies first data masked with a first mask by second data masked with a second mask, and protects the first data and the second data during the multiplying. The multiplying and protecting includes remasking the first data with a third mask, remasking the second data with a fourth mask, executing one or more compensation operations using one or more of the one or more look-up tables, and generating third data masked with a fifth mask. The fifth mask is independent of the first, second, third, and fourth masks. The third data corresponds to the first data multiplied by the second data.

A digital signal processor having at least one streaming address generator, each with dedicated hardware, for generating addresses for writing multi-dimensional streaming data that comprises a plurality of elements. Each at least one streaming address generator is configured to generate a plurality of offsets to address the streaming data, and each of the plurality of offsets corresponds to a respective one of the plurality of elements. The address of each of the plurality of elements is the respective one of the plurality of offsets combined with a base address.

Various embodiments relate to a method for masked decoding of a polynomial a using an arithmetic sharing a to perform a cryptographic operation in a data processing system using a modulus q, the method for use in a processor of the data processing system, including: subtracting an offset δ from each coefficient of the polynomial a; applying an arithmetic to Boolean (A2B) function on the arithmetic shares of each coefficient a.sub.i of the polynomial a to produce Boolean shares â.sub.i that encode the same secret value a.sub.i; and performing in parallel for all coefficients a shared binary search to determine which of coefficients a.sub.i are greater than a threshold t to produce a Boolean sharing value {circumflex over (b)} of the bitstring b where each bit of b decodes a coefficient of the polynomial a.