G06F21/70

Instruction execution that broadcasts and masks data values at different levels of granularity

An apparatus is described that includes an execution unit to execute a first instruction and a second instruction. The execution unit includes input register space to store a first data structure to be replicated when executing the first instruction and to store a second data structure to be replicated when executing the second instruction. The first and second data structures are both packed data structures. Data values of the first packed data structure are twice as large as data values of the second packed data structure. The execution unit also includes replication logic circuitry to replicate the first data structure when executing the first instruction to create a first replication data structure, and, to replicate the second data structure when executing the second data instruction to create a second replication data structure. The execution unit also includes masking logic circuitry to mask the first replication data structure at a first granularity and mask the second replication data structure at a second granularity. The second granularity is twice as fine as the first granularity.

SECURE SENTINEL NETWORK
20230231880 · 2023-07-20 ·

Method and apparatus for protecting computer resources from malicious attack including baseline sentinels and warrior sentinels. Baseline sentinels are deployed on a network serving only as decoys and containing no company data. When any attempt to communicate with a baseline sentinel is detected, a host of warrior sentinels (also containing no company data) are deployed to act as additional decoys, diminishing the chance that a malicious attack will reach a valuable computer resource and collecting information on the malicious attacker. Once the malicious attack stops or is defeated, the warrior sentinels are retired and the system resets to baseline sentinels.

System and method for through window personal cloud transmission

A radio frequency (RF) front end device has a signal traveling from a first antenna to a second antenna in an uplink path and a signal traveling from a third antenna to a fourth antenna in a downlink path. The device is under the control of automatic on/off controller (AOOC) which upon receiving a signal indication from a receive signal detector and amplifier (RSDA) turns on the operations of power amplifier (PA) and simultaneously turns off a low noise amplifier (LNA). This LNA is turned off when the power amplifier is turned on to prevent uplink path and downlink path forming a feedback loop which would result in oscillation, noise and interference.

System and method for through window personal cloud transmission

A radio frequency (RF) front end device has a signal traveling from a first antenna to a second antenna in an uplink path and a signal traveling from a third antenna to a fourth antenna in a downlink path. The device is under the control of automatic on/off controller (AOOC) which upon receiving a signal indication from a receive signal detector and amplifier (RSDA) turns on the operations of power amplifier (PA) and simultaneously turns off a low noise amplifier (LNA). This LNA is turned off when the power amplifier is turned on to prevent uplink path and downlink path forming a feedback loop which would result in oscillation, noise and interference.

Secure processor and a program for a secure processor
11550962 · 2023-01-10 · ·

The instruction code including an instruction code stored in the area where the encrypted instruction code is stored in a non-rewritable format is authenticated using a specific key which is specific to the core where the instruction code is executed or an authenticated key by a specific key to perform an encryption processing for the input and output data between the core and the outside.

Secure processor and a program for a secure processor
11550962 · 2023-01-10 · ·

The instruction code including an instruction code stored in the area where the encrypted instruction code is stored in a non-rewritable format is authenticated using a specific key which is specific to the core where the instruction code is executed or an authenticated key by a specific key to perform an encryption processing for the input and output data between the core and the outside.

SYSTEMS AND METHODS FOR AUTHENTICATING COMPONENTS ON AN ELECTRONIC DEVICE

In some examples, a method comprises determining, at an electronic device having a first component of a first component type, a unique identifier associated with the first component. In some examples, in accordance with a determination that the unique identifier does not match the expected identifier of the component of the first component type in the electronic device, determining that the first component associated with the unique identifier satisfies one or more eligibility criteria. In some examples, in accordance with the determination that the first component associated with the unique identifier satisfies the one or more eligibility criteria, authenticating an association of the first component with the electronic device, including updating an installation counter associated with the first component, and updating the expected identifier for the component of the first type based on the unique identifier of the first component.

APPARATUS AND METHOD FOR VERIFYING INTEGRITY OF HARDWARE BOARD

Disclosed herein are an apparatus and method for verifying the integrity of a hardware board. The apparatus includes one or more processors and execution memory for storing at least one program that is executed by the processors, wherein the program is configured to compare images of components arranged on a verification target board and a source board in a first image, obtained by photographing the verification target board, and in a second image prestored for the source board, as to whether images of the components are identical to each other, and compare first firmware extracted from the verification target board with second firmware of the source board, as to whether first firmware is identical to second firmware and verify integrity of the verification target board based on whether the images are identical to each other and on whether the pieces of firmware are identical to each other.

APPARATUS AND METHOD FOR VERIFYING INTEGRITY OF HARDWARE BOARD

Disclosed herein are an apparatus and method for verifying the integrity of a hardware board. The apparatus includes one or more processors and execution memory for storing at least one program that is executed by the processors, wherein the program is configured to compare images of components arranged on a verification target board and a source board in a first image, obtained by photographing the verification target board, and in a second image prestored for the source board, as to whether images of the components are identical to each other, and compare first firmware extracted from the verification target board with second firmware of the source board, as to whether first firmware is identical to second firmware and verify integrity of the verification target board based on whether the images are identical to each other and on whether the pieces of firmware are identical to each other.

ROLE-BASED COMPONENT ACCESS CONTROL

Component access control includes: receiving, by an access control module, permissions specifying authorization of physical access to one or more secured components of a computing system by one or more requestors; receiving, by the access control module from a requestor, a request to physically access one of the secured components of the computing system; determining, by the access control module based on the permissions, whether the requestor is authorized to physically access the secured component; and responsive to determining that the requestor is authorized to physically access the secured component, granting the requestor physical access to the secured component while prohibiting the requestor from physically accessing other secured components of the computing system.