The subject matter of this specification can be embodied in, among other things, a method that includes receiving at a computing device that is in a locked state, one or more user inputs to unlock the device and to execute at least one command that is different from a command for unlocking the device. The method further includes executing in response to the user inputs to unlock the device an unlocking operation by the device to convert the device from a locked state to an unlocked state. The method further includes executing the at least one command in response to receiving the user inputs to execute the at least one command. The at least one command executes so that results of executing the at least one command are first displayed on the device to a user automatically after the device changes from the locked state to the unlocked state.

The subject matter of this specification can be embodied in, among other things, a method that includes receiving at a computing device that is in a locked state, one or more user inputs to unlock the device and to execute at least one command that is different from a command for unlocking the device. The method further includes executing in response to the user inputs to unlock the device an unlocking operation by the device to convert the device from a locked state to an unlocked state. The method further includes executing the at least one command in response to receiving the user inputs to execute the at least one command. The at least one command executes so that results of executing the at least one command are first displayed on the device to a user automatically after the device changes from the locked state to the unlocked state.

Techniques for providing data protection in an integrated circuit are provided. A method according to these techniques includes exchanging messages with an off-chip, non-volatile memory to securely initialize an anti-replay counter (ARC) value in the integrated circuit based on an ARC value stored in the off-chip, non-volatile memory, and maintaining the ARC value stored in the integrated circuit such that the ARC value stored in the integrated circuit remains synchronized with the ARC value stored in the off-chip, non-volatile memory.

Techniques for providing data protection in an integrated circuit are provided. A method according to these techniques includes exchanging messages with an off-chip, non-volatile memory to securely initialize an anti-replay counter (ARC) value in the integrated circuit based on an ARC value stored in the off-chip, non-volatile memory, and maintaining the ARC value stored in the integrated circuit such that the ARC value stored in the integrated circuit remains synchronized with the ARC value stored in the off-chip, non-volatile memory.

A method for generating a data set on an integrated circuit including programmable resistance memory cells includes applying a forming pulse to all members of a set of the programmable resistance memory cells. The forming pulse has a forming pulse level characterized by inducing a change in resistance in a first subset of the set from an initial resistance range to an intermediate resistance range, while after the forming pulse a second subset of the set has a resistance outside the intermediate range. The method includes applying a programming pulse to the first and second subsets. The programming pulse has a programming pulse level characterized by inducing a change in resistance of the first subset from the intermediate range to a first final range, while after the programming pulse the second subset has a resistance in a second final range, whereby the first and second subsets store said data set.

A method for generating a data set on an integrated circuit including programmable resistance memory cells includes applying a forming pulse to all members of a set of the programmable resistance memory cells. The forming pulse has a forming pulse level characterized by inducing a change in resistance in a first subset of the set from an initial resistance range to an intermediate resistance range, while after the forming pulse a second subset of the set has a resistance outside the intermediate range. The method includes applying a programming pulse to the first and second subsets. The programming pulse has a programming pulse level characterized by inducing a change in resistance of the first subset from the intermediate range to a first final range, while after the programming pulse the second subset has a resistance in a second final range, whereby the first and second subsets store said data set.

Systems and methods are disclosed for securing an information handling system. A method for securing an information handling system may include securing the information handling system in an enclosure with a locking mechanism of a bezel; receiving a request to unlock the bezel at a baseboard management controller (BMC), the BMC communicatively coupled to the bezel; retrieving a first artifact stored in a trusted platform module (TPM) in response to the request; attempting to authorize the request using the first artifact; and unlocking the locking mechanism if the request is authorized.

Systems and methods are disclosed for securing an information handling system. A method for securing an information handling system may include securing the information handling system in an enclosure with a locking mechanism of a bezel; receiving a request to unlock the bezel at a baseboard management controller (BMC), the BMC communicatively coupled to the bezel; retrieving a first artifact stored in a trusted platform module (TPM) in response to the request; attempting to authorize the request using the first artifact; and unlocking the locking mechanism if the request is authorized.

A data processing system is provided with processing circuitry as well as a bank of 64-bit registers. An instruction decoder decodes arithmetic instructions and logical instruction specifying arithmetic operations and logical operations to be performed upon operands stored within the 64-bit registers. The instruction decoder is responsive to an operand size field SF within the arithmetic instructions and the logical instructions specifying whether the operands are 64-bit operands or 32-bit operands where all of the operands are 64-bit operands or all of the operands are 32-bit operands. If a switch is made to a lower exception level, then a check is made as to whether or not a register being used was previously subject to a 64-bit write to that register. If such a 64-bit write had previously taken place, then the upper 32-bits are flushed so as to avoid data leakage from the higher exception level.

A data processing system is provided with processing circuitry as well as a bank of 64-bit registers. An instruction decoder decodes arithmetic instructions and logical instruction specifying arithmetic operations and logical operations to be performed upon operands stored within the 64-bit registers. The instruction decoder is responsive to an operand size field SF within the arithmetic instructions and the logical instructions specifying whether the operands are 64-bit operands or 32-bit operands where all of the operands are 64-bit operands or all of the operands are 32-bit operands. If a switch is made to a lower exception level, then a check is made as to whether or not a register being used was previously subject to a 64-bit write to that register. If such a 64-bit write had previously taken place, then the upper 32-bits are flushed so as to avoid data leakage from the higher exception level.