Provided is a method for optimizing a lithography quality, including: determining a wave function stray term introduced by a surface roughness of a metal film layer based on Eigen matrix method and Bloch theorem; inputting the wave function stray term into a lithography quality deviation mathematical model for calculation and simulation to obtain an influence analysis curve of a roughness of the metal film layer on a lithography quality, the influence analysis curve characterizes an influence result of the roughness of the metal film layer on the lithography quality; reducing the surface roughness of the metal film layer and/or providing a metal-dielectric multilayer film structure between a mask above a metal-dielectric unit and air according to the influence result, so as to optimize the lithography quality of the metal-dielectric unit. Provided is an apparatus for optimizing a lithography quality, an electronic device, a computer-readable storage medium and computer program product.

Within a layout of a first surface in a flip chip configuration, a bump restriction area is mapped according to a set of bump placement restrictions, wherein a first bump placement restriction specifies an allowed distance range between a bump and a qubit chip element in a layout of the first surface, and wherein a second bump placement restriction specifies an allowed distance range between the bump and a qubit chip element in a layout of a second surface in the flip chip configuration. An electrically conductive material is deposited outside the bump restriction area, to form the bump, wherein the bump comprises an electrically conductive structure that electrically couples a signal between the first surface and the second surface and is positioned according to the set of bump placement restrictions.

In some embodiments, an apparatus and a system, as well as a method and article, may operate to model electromagnetic data to provide modeled electromagnetic data by solving a first set of surface integral equations that include earth model parameters corresponding to an earth model of a geological formation. Additional activity may include publishing at least some of the modeled electromagnetic data in human-readable form, and/or controlling drilling operations in the geological formation based on the earth model when error between the modeled electromagnetic data and measured electromagnetic data is less than a selected threshold. Additional apparatus, systems, and methods are disclosed.

System and method that allow to control density distributions of multiple particles (micro-or-nano-sized objects) to desired positions are described. A kernel density estimation (KDE) is used as a proxy for the initial particle density distribution and an optimal control problem is defined and solved using this approximation. A sequence of electrode electric potentials is computed so that the initial particle distribution is shaped into a target distribution after applying this sequence over time. The optimal control cost function is defined in terms of an L2 metric, with the L2 function that is used to compute the error between the particle density at the end of a time horizon and a target density. The KDE depends on the predicted trajectories of a set of particles, where the trajectory of a single particle is determined by a lumped, 2D, capacitive-based, nonlinear model describing the particle's motion.

Roughly described, a system for estimating an effective channel length of a 3D transistor having a gate length below 20 nm involves estimating an effective volume of the channel and a cross-sectional area of the channel, and estimating the effective channel length as the ratio of effective volume to cross-sectional area. Preferably the effective volume is estimated as the sum of the Voronoi volumes within containing boundaries of the channel, excluding those volumes having a dopant concentration above the source/drain dopant concentration at the carrier injection point. The containing boundaries can be identified using geometry data describing the transistor, particularly the data identifying inner surfaces of the gate dielectric. The estimated effective channel length can be used in TCAD level analysis of the transistor and calculating characteristics of the transistor as needed for circuit simulation.

An integrated circuit design tool includes a cell library. The cell library includes entries for a plurality of cells, entries in the cell library including specifications of particular cells in a computer executable language. At least one entry in the cell library can comprise a specification of physical structures and timing parameters of a plurality of transistors and an interconnect; wherein a transistor in the plurality has a channel comprising one or more nanowires or 2D material strips arranged in parallel, and the interconnect comprises one or more nanowires or 2D material strips arranged in parallel and connected to terminals of more than one of the transistors in the plurality of transistors. An integrated circuit including the plurality of transistors and the interconnect is described.

A method of designing a nano-rectenna panel (NRP) of a vehicle includes generating one or more performance benchmarks associated with nano-rectenna devices that comprise the NRP. A material for the nano-rectenna devices is identified based on one or more of the one or more performance benchmarks. The method also includes designing the NRP based on the material.

Various embodiments of the present technology provide for the ultra-high density heterogenous integration, enabled by nano-precise pick-and-place assembly. For example, some embodiments provide for the integration of modular assembly techniques with the use of prefabricated blocks (PFBs). These PFBs can be created on one or more sources wafers. Then using pick-and-place technologies, the PFBs can be selectively arranged on a destination wafer thereby allowing Nanoscale-aligned 3D Stacked Integrated Circuit (N3-SI) and the Microscale Modular Assembled ASIC (M2A2) to be efficiently created. Some embodiments include systems and techniques for the construction of construct semiconductor devices which are arbitrarily larger than the standard photolithography field size of 26?33 mm, using pick-and-place assembly.

An integrated circuit design tool includes a cell library. An entry in the cell library comprises a specification of the cell including a first transistor and a second transistor. The first transistor can include a first set of nanowires or 2D material strips arranged in parallel to form a channel structure, and a gate conductor disposed across the first set of nanowires or 2D material strips. The second transistor can include a second set of nanowires or 2D material strips arranged in parallel to form a channel structure, and a gate conductor disposed across the first set of nanowires or 2D material strips. The number of nanowires or 2D material strips in the first set can be different from the number of nanowires or 2D material strips in the second set, so that the drive power of the individual transistors can be set with finer granularity.

An integrated circuit design tool for modeling resistance of an interconnect specifies a structure of the interconnect in a data structure in memory in or accessible by the computer system using 3D coordinate system. For each of a plurality of volume elements in the specified structure, the tool specifies a location and one of first and second materials of the interconnect having specified resistivities, and for each volume element generates a model resistivity for the volume element as a function of resistivity of volume elements within a neighborhood of the volume element and a specified transition region length .