A method for determining a housing capable of accommodating waste heat generating electronic components on a printed circuit board includes: detecting an arrangement of the electronic components on a mounting side of the printed circuit board; determining several functional areas within the mounting side in which at least one of the electronic components is arranged according to the detected arrangement; assigning a thermal function to each of the functional areas, each of the thermal functions comprising: a function for generating waste heat due to a power dissipation of the at least one electronic component arranged in a respective functional area according to the detected arrangement during operation, and a maximum temperature up to which the at least one electronic component arranged in the respective functional area is operable without damage and performance limitation.

Embodiments include herein are directed towards a method for use in an electronic design environment is provided. Embodiments may include receiving, using a processor, an electronic design and providing, at a graphical user interface, an option to change an object associated with the electronic design. Embodiments may further include identifying a damage area associated with the electronic design, the damage area including an object therein. Embodiments may also include generating a polygon for the damage area and caching one or more voids located outside of the damage area. Embodiments may further include performing a cut and stamp operation on a portion of the electronic design associated with the damage area and populating, at the graphical user interface, a repaired damage area.

A method of estimating warpage of an interposer and a method of manufacturing a semiconductor package by using the same are disclosed. The interposer includes a through electrode passing through a substrate, and a plurality of metal wiring layers and a plurality of insulating layers on the substrate, and the method of estimating warpage of an interposer includes: performing a temperature sweep test by using sample interposers, and measuring warpages according to temperatures; deriving a warpage slope, as a function of temperature, of each of the sample interposers; deriving a warpage model by linearly fitting the warpage slope with respect to an average pattern density of metal wiring layers in each of the sample interposers; and calculating a room temperature warpage reference value of the interposer based on the warpage model.

Package design method for semiconductor chip package for high speed SerDes signals for optimization of package differential impedance and reduction of package differential insertion loss and differential return loss at data rates of 25 to 60 Gb/s and beyond. The method optimizes parameters of vertical interconnections of BGA ball, via, and PTH, and around the joint between vertical and horizontal interconnections of traces. Also disclosed are examples of chip package designs for high speed SerDes signals, including one using 0.8 mm BGA ball pitch and 10-layer buildup substrate, one using 1 mm BGA ball pitch and 14-layer buildup substrate, one using 6-layer buildup substrate with signals routed on top and bottom metal layers with microstrip line structure, and one using 12-layer package substrate with unique via configuration, all of which achieve low substrate differential impedance discontinuity, reduced differential insertion loss and differential return loss between BGA balls and C4 bumps.

A method of estimating warpage of an interposer and a method of manufacturing a semiconductor package by using the same are disclosed. The interposer includes a through electrode passing through a substrate, and a plurality of metal wiring layers and a plurality of insulating layers on the substrate, and the method of estimating warpage of an interposer includes: performing a temperature sweep test by using sample interposers, and measuring warpages according to temperatures; deriving a warpage slope, as a function of temperature, of each of the sample interposers; deriving a warpage model by linearly fitting the warpage slope with respect to an average pattern density of metal wiring layers in each of the sample interposers; and calculating a room temperature warpage reference value of the interposer based on the warpage model.

A method, apparatus and computer program products are provided for determining an entry finder from a plurality of merge points of a bounding box for optimal performance of differential group pattern match routing. One example method includes identifying each of a plurality of merge point candidates, performing a routability determination process, the results of the routability determination process comprising a remaining subset of the plurality of merge point candidates, routing each remaining merge point from the remaining subset of the plurality of merge point candidates, calculating a routing cost for each remaining merge point from the remaining subset of the plurality of merge point candidates, and determining a merge point having a lowest calculated cost.

The present invention discloses a simulation processor for simulating a system comprising a system component. The simulation processor comprises a memory die and a logic die. The memory die comprises a look-up table circuit (LUT) for storing data related to a mathematical model of the system component. The logic die comprises an arithmetic logic circuit (ALC) for performing arithmetic operations on the model-related data. The memory die and the logic die are located in a same package.

Semiconductor device design methods and conductive bump pattern enhancement methods are disclosed. In some embodiments, a method of designing a semiconductor device includes designing a conductive bump pattern design, and implementing a conductive bump pattern enhancement algorithm on the conductive bump pattern design to create an enhanced conductive bump pattern design. A routing pattern is designed based on the enhanced conductive bump pattern design. A design rule checking (DRC) procedure is performed on the routing pattern.

A chip module, including a radio frequency integrated circuit (RFIC) chip and a package, and a method and system for designing the module. Chip and package design are performed so the RF front end (FE) is split between chip and package. The chip includes an amplifier with a first differential port and the package includes a passive device and matching network with a second differential port connected to the first differential port. The second differential port is power matched to the first differential port using complex power matching based on port voltage reflection coefficients in order to achieve improved performance (i.e., a peak power transfer across a bandwidth as opposed to at only one frequency). The power matching process can result in a chip power requirement reduction that allows for device size scaling. Thus, designing the chip and designing the package is iteratively repeated in a chip-package co-optimization process.

A method includes receiving a first design for conductive bumps on a first surface of an interposer, the conductive bumps in the first design having a same cross-section area; grouping the conductive bumps in the first design into a first group of conductive bumps in a first region of the first surface and a second group of conductive bumps in a second region of the first surface, where a bump pattern density of the second region is lower than that of the first region; forming a second design by modifying the first design, where modifying the first design includes modifying a cross-section area of the second group of conductive bumps in the second region; and forming the conductive bumps on the first surface of the interposer in accordance with the second design, where after being formed, the first group of conductive bumps and the second group of conductive bumps have different cross-section areas.