Within a layout of a first surface in a flip chip configuration, a bump restriction area is mapped according to a set of bump placement restrictions, wherein a first bump placement restriction specifies an allowed distance range between a bump and a qubit chip element in a layout of the first surface in the flip chip configuration. An electrically conductive material is deposited outside the bump restriction area, to form the bump, wherein the bump comprises an electrically conductive structure that electrically couples a signal from the first surface and is positioned according to the set of bump placement restrictions.

A method and apparatus for identifying net text in a net list at each hierarchical level of the net list is disclosed. The identified net text is then associated with the hierarchical level in which the net text was found. Each cell in the net list can then be optimized by exploding the net list of at least one cell. Once exploded, the identified net text together with the associated hierarchical level of each progeny cell of each exploded cell is associated with the net list of the exploded cell.

A method of evaluating sampling sizes for circuit simulation comprises generating a plurality of coverage scenarios based on a defect universe, determining a coverage amount for each of the plurality of coverage scenarios, and associating the plurality of coverage scenarios with a plurality of bins based on the coverage amount for each of the plurality of coverage scenarios. The method further comprises sampling, with a first sampling size, each of the coverage scenarios to determine first sampled coverage scenarios, and determining an error value for each of the plurality of coverage scenarios based on the coverage amount of each of the plurality of coverage scenarios and a coverage amount of a respective one of the first sampled coverage scenarios. Further, the method comprises generating, with a processor and for the first sampling size, a confidence score for each of the plurality of bins based on the error value for each of the plurality of coverage scenarios, and outputting the confidence score for each of the plurality of bins.

According to an aspect, a semiconductor design system includes at least one neural network including a first predictive model and a second predictive model, where the first predictive model is configured to predict a first characteristic of a semiconductor device, and the second predictive model is configured to predict a second characteristic of the semiconductor device. The semiconductor design system includes an optimizer configured to use the neural network to generate a design model based on a set of input parameters, where the design model includes a set of design parameters for the semiconductor device such that the first characteristic and the second characteristic achieve respective threshold conditions.

Machine assisted systems and methods for enhancing the resolution of an IC thermal profile from a system analysis are described. These systems and methods can use a neural network based predictor, that has been trained to determine a temperature rise across an entire IC. The training of the predictor can include generating a representation of two or more templates identifying different portions of an integrated circuit (IC), each template associated with location parameters to position the template in the IC; performing thermal simulations for each respective template of the IC, each thermal simulation determining an output based on a power pattern of tiles of the respective template, the output indicating a change in temperature of a center tile of the respective template relative to a base temperature of the integrated circuit; and training a neural network. The trained predictor can be used to determine a temperature rise and then can be appended to a system level thermal profile of the IC to generate a detailed thermal profile of the IC.

A method of evaluating sampling sizes for circuit simulation comprises generating a plurality of coverage scenarios based on a defect universe, determining a coverage amount for each of the plurality of coverage scenarios, and associating the plurality of coverage scenarios with a plurality of bins based on the coverage amount for each of the plurality of coverage scenarios. The method further comprises sampling, with a first sampling size, each of the coverage scenarios to determine first sampled coverage scenarios, and determining an error value for each of the plurality of coverage scenarios based on the coverage amount of each of the plurality of coverage scenarios and a coverage amount of a respective one of the first sampled coverage scenarios. Further, the method comprises generating, with a processor and for the first sampling size, a confidence score for each of the plurality of bins based on the error value for each of the plurality of coverage scenarios, and outputting the confidence score for each of the plurality of bins.

The present invention relates to the design of a Power Delivery Network (PDN) of a system of VRM-Board-Decoupling Capacitances-Package-Chip for the nm-CMOS devices that typically suffers from the resonances, transient oscillations, and voltage Decay, which resulted in the device fails the specification that often considered as a design flaw and leads to the costly devices respins. Present invention provides a new method, an apparatus or Tool, and a process to design PDN without noted deficiencies, which achieved by damping PDN at setting elevated impedances, in contrast with the common practice of lowering them, which improves the devices performance and reduces the rate of the chips respins. This invention also includes an advanced process that enable to start design early and simultaneously by different engineering groups without disclosing the proprietary information which they might have.

A global computer aided engineering (CAE) model representing an electronic product that contains solder joints and an individual detailed solder joint model are received. The solder joint model can include a solder ball, one or more metal pads, a portion of printed circuit board, and a portion of semiconductor chip component. The global CAE model includes locations of the solder joints to be evaluated in a drop test simulation. The solder joint model is replicated at each location to create a local CAE model via a geometric relationship between the global CAE model and the local CAE model. Simulated physical behaviors of the product under a design condition are obtained in a co-simulation using the global CAE model in a first time scale and the local CAE model in a second time scale. Simulated physical behaviors are periodically synchronized based on kinematic and force constraints.

A method for path routing according to an embodiment of the present disclosure may include selecting a first start point and a first end point with which path routing is performed in a circular frame generated by connecting all points included in one or more start point sets included in a layer, one or more end point sets paired with the start point set, and one or more edge point pair sets to one closed curve, generating a connectivity graph by connecting edge points included in one or more nodes corresponding to segments obtained by dividing the circular frame into one or more regions, and connecting the first start point and the first end point based on a cost for connecting the first start point and the first end point calculated using the connectivity graph.

Various aspects of the present disclosure generally relate to wireless communication. In some aspects, a device may receive layout information that identifies a configuration of an antenna array of antennas, wherein the antenna array is to include a plurality of antenna subarrays and a plurality of antenna chips, wherein each antenna chip is communicatively coupled to antennas of an associated antenna subarray; determine, based at least in part on a phase shift characteristic associated with the antennas, a set of phase differences between antenna subarrays; determine, based at least in part on the set of phase differences, a chip position of each antenna chip relative to the associated antenna subarray; and generate, based at least in part on the chip position of each antenna chip, a layout of an antenna package to receive the antenna array and the plurality of antenna chips. Numerous other aspects are provided.