Systems and methods for application specific integrated circuit design using Chronos Links are disclosed. A Chronos Link is an ASIC on-chip and off-chip interconnect communication protocol that allows interfaces to transmit and receive information. The protocol may utilize messages or signals to indicate the availability and/or readiness of information to be exchanged between a producer and a consumer allowing the communication to be placed on hold and to be resumed seamlessly. A method includes inserting gaskets and channel repeaters connected to interfaces of multiple intellectual property (IP) blocks in order to replace traditional links with Chronos Links; performing simplified floorplanning; performing simplified placement; performing simplified clock tree synthesis (CTS) and routing; and performing simplified timing closure.

Embodiments herein provide for reverse engineering of integrated circuits (ICs) for design verification. In example embodiments, an apparatus receives a gate-level netlist for an integrated circuit (IC), generates a list of equivalence classes related to signals included in the gate-level netlist, determines control signals of the gate-level netlist based at least in part on the list of equivalence classes, determines a logic flow of a finite state transducer (FST) based at least in part on the control signals, and generates register transfer level (RTL) source code for the IC based on the FST.

Systems and methods are disclosed that implement a tool for executing performance-aware topology synthesis of a network, such as a network-on-chip (NoC). The tool is provided with network information. The tool uses the network information to automatically determine data width and clock speed for each element in the network that meet the network's constraints and performance requirements. The tool is able to provide the performance-aware topology synthesis rapidly, while honoring the objectives and the network's constraints.

System and methods are disclosed to qualify networks properties and that can be used for topology synthesis of networks, such as a network-on-chip (NoC). In accordance with various embodiments and different aspects of the invention, quality metric are generated, analyzed, and used to determine a quantitative quality set of values for a given generated solution for a network. The method disclosed allows the network designer or an automated network generation process to understand if the results produced are a good, an average or a bad solution. The advantage of the invention includes simplification of design process and the work of the designer by using quality metrics. Various quality metrics are generated using network definitions. These quality metrics provide quality evaluation and the quality assessment of the optimization process for a generated (optimized) network. The quality metrics include analyzing latency through a network and analyzing total wore length used by the network.

A power profile for an electronics design is implemented by accessing a unit descriptive of an electronic design comprising a first intellectual property (IP) block expressed in a simulation language and comprising a netlist. A total number (NT) of net weights are identified in the netlist, wherein each respective net weight is proportional to an effective load capacitance of an associated net. A total number (NP) of populated nets having associated toggle simulation data are identified in the netlist. A ratio (KS) equal to a sum of all NT net weights divided by a sum of all NP populated net weights is generated. A sample energy (ES) is generated based on the associated toggle simulation data of and net weights for each of the NP populated nets. And a block power profile is modelled based on an estimated block energy (EN) equal to KS multiplied by ES.

A system and method for adding interface protection to an electronic design using parameters. The electronic design and interface protection scheme are defined as parameters. An interface protection model creates interface protection implementation parameters that describe the implementation details of the interface protection. A hardware description model uses the electronic design parameters and the interface protection implementation parameters to create a hardware description. The interface protection scheme can be a built-in protection scheme, a user defined scheme, a scheme that includes place holders that the user may define later, and a combination of the preceding. The interface protection scheme may contain components to help with the retiming of the description of hardware.

Systems and methods for assembling and developing a System-on-a-chip (SoC) by using templates and designer input data are described. One of the methods includes receiving a request for generating a design of the SoC. In response to the request, a template database is accessed to provide templates of a plurality of designs of systems-on-chips (SoCs). Each of the templates is for a technology application. The method includes receiving a selection of one of the templates. The one of the templates represents components of the SoC. The method also includes receiving a configuration file including configuration data input for the components of the SoC. The method includes compiling the configuration file and a definition file for the SoC to generate design files for the SoC.

On-the-fly multi-bit flip-flop (MBFF) generation is provided by selecting at least two flip-flop blocks from a plurality of candidate flip-flop blocks; identifying a control block from a plurality of candidate control blocks, the control block being identified based on operational specifications of the selected flip-flop blocks; and generating a multi-bit flip-flop instance based on the selected flip-flop blocks and the identified control block.

Computer-implemented systems and methods for automatically generating an electronic circuit IP block are provided. The disclosed systems and methods maintain the process design rules (DRC Clean), connectivity (LVS Clean) correctness, and obey Reliability Verification (RV) and DFM (Design for Manufacturability) constraints, including time constraints. Exemplary systems and methods may include an electronic circuit layout generator and/or IP generator to obtain manufacturing processes and design rules from an external source, define a type of electronic circuit to be fabricated, prepare a circuit schematic of the defined electronic circuit, and generate an IP block for the defined electronic circuit based on the circuit schematic. A computer program generator is provided to create the defined electronic circuit. A computer readable storage medium contains processing instructions for obtaining the manufacturing processes and design rules and for fabricating the electronic circuit.

A method of generating an IC layout diagram includes positioning a cell in the IC layout diagram relative to a first metal layer cut region alignment pattern and overlapping the cell with a first metal layer cut region. The cell includes a first metal layer region corresponding to one of a first or second mask set, the first metal layer cut region alignment pattern includes a sub-pattern corresponding to the one of the first or second mask set, and the first metal layer cut region corresponds to the sub-pattern.