The invention comprises (i) a compilation method for automatically converting a single-threaded software program into an application-specific supercomputer, and (ii) the supercomputer system structure generated as a result of applying this method. The compilation method comprises: (a) Converting an arbitrary code fragment from the application into customized hardware whose execution is functionally equivalent to the software execution of the code fragment; and (b) Generating interfaces on the hardware and software parts of the application, which (i) Perform a software-to-hardware program state transfer at the entries of the code fragment; (ii) Perform a hardware-to-software program state transfer at the exits of the code fragment; and (iii) Maintain memory coherence between the software and hardware memories. If the resulting hardware design is large, it is divided into partitions such that each partition can fit into a single chip. Then, a single union chip is created which can realize any of the partitions.

System and methods are disclosed to qualify networks properties and that can be used for topology synthesis of networks, such as a network-on-chip (NoC). In accordance with various embodiments and different aspects of the invention, quality metric are generated, analyzed, and used to determine a quantitative quality set of values for a given generated solution for a network. The method disclosed allows the network designer or an automated network generation process to understand if the results produced are a good, an average or a bad solution. The advantage of the invention includes simplification of design process and the work of the designer by using quality metrics. Various quality metrics are generated using network definitions. These quality metrics provide quality evaluation and the quality assessment of the optimization process for a generated (optimized) network. The quality metrics include analyzing latency through a network and analyzing total wore length used by the network.

A software-based (“soft”) real-time hub designed and implemented for use in simulation (or control testing) systems such as to provide a modular soft-real-time PIL. A simulation system of the present description typically may include one or more of the following useful subsystems or components: (a) a soft-real-time hub; (b) simulation interfaces; and (c) hardware emulation subsystems/devices. The soft-real-time hub is typically a combination of hardware and software adapted to provide deterministic data transport between simulations and input/output (I/O) emulation. By creating a common point, the hub enables simulation modules to be swapped out as the simulation system progresses without the operator having to worry about interface timing, forcing, or data visualization. A desirable aspect of the simulation system is it allows for testing certain conditions by forcing I/O and then seeing how the controller or system under testing responds.

A method, computer program product, and/or system is disclosed for testing integrated circuits, e.g., processors, that includes: generating a software design prototype of the functional behavior of an integrated circuit to be tested; creating a lab All-Events-Trace (AET) normalized model of the integrated circuit, wherein the normalized model captures the functions of the integrated circuit and not the non-functional aspects of the integrated circuit; generating a lab scenario using the software design prototype and the AET normalized model of the integrated circuit for a particular cycle of interest, wherein the lab scenario contains initialization for all signals that have hardware information; and generating a replayed lab normalized AET for the particular cycle of interest.

A method for path routing according to an embodiment of the present disclosure may include selecting a first start point and a first end point with which path routing is performed in a circular frame generated by connecting all points included in one or more start point sets included in a layer, one or more end point sets paired with the start point set, and one or more edge point pair sets to one closed curve, generating a connectivity graph by connecting edge points included in one or more nodes corresponding to segments obtained by dividing the circular frame into one or more regions, and connecting the first start point and the first end point based on a cost for connecting the first start point and the first end point calculated using the connectivity graph.

An integrated circuit including a plurality of standard cells is provided. The integrated circuit includes a first standard cell group including at least two first standard cells, a second standard cell group adjacent to the first standard cell group in a first direction, the second standard cell group including at least one second standard cell, and a first insulating gate bordered by one side of at least one of the first standard cells and one side of the at least one second standard cell, wherein each of the first and second standard cells includes a p-type transistor (pFET) and an n-type transistor (nFET) which are integrated, wherein each of the first and second standard cells has first wiring lines of different designs, and wherein each of the first and second standard cells has the same or different placement of an active region according to the corresponding design.

Creating an adaptable dynamic region for hardware acceleration can include receiving a first kernel for inclusion in a circuit design for an integrated circuit of an accelerator platform. The circuit design includes a dynamic design corresponding to a dynamic region of programmable circuitry in the integrated circuit that couples to a static region of the programmable circuitry. The first kernel can be included in the within the dynamic design. A global resource used by the first kernel can be determined. An interconnect architecture for the dynamic design can be constructed based on the global resource used by the first kernel.

An extensible processor including define d function block for executing instruction implemented control logic or finite state machine. The defined function block can be executed without initiation by a software instruction stream.

An infusion pump assembly includes a reservoir assembly configured to contain an infusible fluid. A motor assembly is configured to act upon the reservoir assembly and dispense at least a portion of the infusible fluid contained within the reservoir assembly. Processing logic is configured to control the motor assembly. The processing logic includes a primary microprocessor configured to execute one or more primary applications written in a first computer language; and a safety microprocessor configured to execute one or more safety applications written in a second computer language.

A method for performing automated detection of transaction latency for a processor design model running an application in a hardware simulation accelerator. The method includes loading the processor design model into the hardware simulation accelerator, loading the application into the processor design model running within the hardware simulation accelerator, simulating the processor design model running the application within the hardware simulation accelerator, and for each individual transaction of the application: establishing a first checkpoint at a start of an execution of the individual transaction by creating a breakpoint and resetting a counter, establishing a second checkpoint at a completion of the transaction by creating another breakpoint and obtaining latency information for the second checkpoint. The latencies of the individual transaction from the start to the completion are measured based on the latency information.