Patent classifications
G06F2115/10
Quality metrics for optimization tasks in generation of a network
Qualifying networks properties that can be used for topology generation of networks, such as a network-on-chip (NoC). In accordance with various embodiments and different aspects of the invention, quality metrics are generated, analyzed, and used to determine a quantitative quality set of values for a given generated solution for a network. The method disclosed allows the network designer or an automated network generation process to determine if the results produced are a good, an average or a bad solution. The advantage of the invention includes simplification of design process and the work of the designer by using quality metrics. Various quality metrics are generated using network definitions. These quality metrics provide quality evaluation and the quality assessment of the optimization process for a generated (optimized) network. The quality metrics include analyzing latency through a network and analyzing total wire length used by the network.
Computer system for designing a process unit
A computer system for designing a process unit, the process unit comprising a set of unit operations interconnected by streams. The computer system comprises a stream generator (process simulator) configured to simulate the process unit by modelling the set of unit operations and flow conditions of each of the streams that interconnect the unit operations within the process unit. The stream generator generates physical properties of each of the streams based on their respective generated flow conditions. The computer system further comprises a stream engineering properties module configured to determine stream engineering properties of each of the streams based on their respective flow conditions and generated physical properties. The stream engineering properties define engineering requirements of each of the streams. The computer system further comprises a preliminary engineering system configured to determine engineering information based on the determined stream engineering properties, physical properties of each of the streams and flow conditions of each of the streams, wherein the engineering information comprises: equipment engineering data for each of the unit operations and pipe engineering data for each of the streams. The computer system is configured to design the process unit based on interactively integrating the engineering information with the determined stream engineering properties, flow conditions and generated physical properties of the streams through information channels formed by each stream interconnection between a pair of unit operations.
Method and system for converting a single-threaded software program into an application-specific supercomputer
The invention comprises (i) a compilation method for automatically converting a single-threaded software program into an application-specific supercomputer, and (ii) the supercomputer system structure generated as a result of applying this method. The compilation method comprises: (a) Converting an arbitrary code fragment from the application into customized hardware whose execution is functionally equivalent to the software execution of the code fragment; and (b) Generating interfaces on the hardware and software parts of the application, which (i) Perform a software-to-hardware program state transfer at the entries of the code fragment; (ii) Perform a hardware-to-software program state transfer at the exits of the code fragment; and (iii) Maintain memory coherence between the software and hardware memories. If the resulting hardware design is large, it is divided into partitions such that each partition can fit into a single chip. Then, a single union chip is created which can realize any of the partitions.
DATA PATH CIRCUIT DESIGN USING REINFORCEMENT LEARNING
Apparatuses, systems, and techniques for designing a data path circuit such as a parallel prefix circuit with reinforcement learning are described. A method can include receiving a first design state of a data path circuit, inputting the first design state of the data path circuit into a machine learning model, and performing reinforcement learning using the machine learning model to output a final design state of the data path circuit, wherein the final design state of the data path circuit has decreased area, power consumption and/or delay as compared to conventionally designed data path circuits.
Frozen boundary multi-domain parallel mesh generation
A computer-implemented method for meshing a model of a physical electro-magnetic assembly is disclosed. The method includes separating the base mesh of the model into two domains and freezing the boundary between these domains. Each domain is then sent for mesh refinement by separate computer processors. Each computer processor generates a refined mesh of the respective domain without communication between processors. Two-way boundary mesh mapping is then performed, resulting in a global conformal mesh. Surface recovery and identity assignment are then performed by separate computer processors in parallel for each domain, without communication between processors. Related apparatus, systems, techniques, methods and articles are also described.
Signal processor, filter, control circuit for power converter circuit, interconnection inverter system and PWM converter system
A signal processor is configured to perform a process equivalent to performing a series of fixed-to-rotating coordinate conversion, a predetermined process and then rotating-to-fixed coordinate conversion, while maintaining linearity and time-invariance. The signal processor performs a process given by the following matrix G:
Selective exposure of standard cell output nets for improved routing solutions
Provided are embodiments for a computer-implemented method for routing standard cells of an integrated circuit. Embodiments include obtaining a layout of a plurality of standard cells for routing, and determining existing output connections for each of the plurality of standard cells. Embodiments can also include generating a representation for the layout removing the existing output connections for each of the plurality of standard cells; and providing the representation of the layout to an autorouter. Also provided are embodiments for a system and computer program product for routing standard cells of an integrated circuit.
Method to segregate logic and memory into separate dies for thermal management in a multi-dimensional packaging
A packaging technology to improve performance of an AI processing system resulting in an ultra-high bandwidth system. An IC package is provided which comprises: a substrate; a first die on the substrate, and a second die stacked over the first die. The first die can be a first logic die (e.g., a compute chip, CPU, GPU, etc.) while the second die can be a compute chiplet comprising ferroelectric or paraelectric logic. Both dies can include ferroelectric or paraelectric logic. The ferroelectric/paraelectric logic may include AND gates, OR gates, complex gates, majority, minority, and/or threshold gates, sequential logic, etc. The IC package can be in a 3D or 2.5D configuration that implements logic-on-logic stacking configuration. The 3D or 2.5D packaging configurations have chips or chiplets designed to have time distributed or spatially distributed processing. The logic of chips or chiplets is segregated so that one chip in a 3D or 2.5D stacking arrangement is hot at a time.
INTERFERENCE CHANNEL CONTENTION MODELLING USING MACHINE LEARNING
A computer-implemented method of producing a trained Machine Learning based Task Contention Model to predict time delays resulting from contention between tasks running in parallel on a multi-processor system is provided herein. The method includes: executing a plurality of microbenchmarks, μBenchmarks B.sub.j, on the multi-processor system in isolation and measuring at least one resultant Performance Monitoring Counter, PMC, over time to extract ideal characteristic footprints of each μBenchmark when operating in isolation; executing possible pairing scenarios of the plurality of μBenchmarks in parallel on the multi-processor system and measuring the effect on the execution time of each μBenchmark, ΔT.sup.B.sup.
SIGNAL PROCESSOR, FILTER, CONTROL CIRCUIT FOR POWER CONVERTER CIRCUIT, INTERCONNECTION INVERTER SYSTEM AND PWM CONVERTER SYSTEM
A signal processor is configured to perform a process equivalent to performing a series of fixed-to-rotating coordinate conversion, a predetermined process and then rotating-to-fixed coordinate conversion, while maintaining linearity and time-invariance. The signal processor performs a process given by the following matrix G:
where F(s) is a transfer function representing the predetermined process, ω.sub.0 is a predetermined angular frequency and j is the imaginary unit.