A method for obtaining board parameters of a printed circuit board, including the following steps: obtaining parameter information of a stripline on the printed circuit board; obtaining physical parameters of the stripline based on the parameter information of the stripline and a predetermined electromagnetic simulation application; calculating required board parameters of the printed circuit board based on the parameter information and the physical parameters of the stripline. In the present disclosure, the physical parameters of the stripline are obtained based on the physical nature of the stripline on the printed circuit board, and there is no need for fitting or adopting a hypothetical model in order to obtain board parameters corresponding to each frequency point of the stripline; the present disclosure is simple and straightforward during operation, and the obtained board parameters of the printed circuit board are highly accurate.

Tools and techniques are described to automate line testing when wiring devices (such as equipment and sensors) to controllers. Controllers have access to databases of the devices that are controlled by them, including wiring diagrams and protocols, such that the controller can automatically check that each wire responds correctly to stimulus from the controller. After testing, a reporting device rapidly shows the results of the line testing.

An aspect of the disclosed embodiments is a system for printed circuit board (PCB) outline generation including at least one processor configured to receive one or more electronic PCB design files defining a PCB design. The at least one processor is also configured to process the one or more electronic PCB design files to distinguish physical features of the PCB design from non-physical (auxiliary) features of the PCB design. The at least one processor is also configured to generate an estimated physical outline for the PCB design that encompasses the physical features and excludes the auxiliary features. The at least one processor is also configured to electronically store the estimated physical outline in association with the PCB design. Other aspects are included.

A system and methods are disclosed that generate a physical roadmap for the connectivity of a network, such as a network-on-chip (NoC). The roadmap includes a set of possible positions for placement of edges and nodes, which are known to be an acceptable and good position for placement of these network elements, that honors the constraints of the network. These known positions are made available to the system for synthesis of the network and generating the connectivity and placement based on the physical roadmap.

A system and a method are disclosed for placing hardware components on a printed circuit board (“PCB”) in a way that enables all hardware components on the PCB to be passively cooled without using active cooling systems. Components are selected to be placed onto the PCB and heat metrics for each component is obtained (e.g., from a server). The components are ranked based on the amount of heat that each component generates. A corresponding position for each of the hardware components is determined based on the ranking of the components and the orientation of the PCB. The placement is based on the concept that air having higher temperature rises while air having cooler temperature falls. A representation of the PCB according to corresponding positions of the hardware components may be generated for display.

Inter-alia, a method for manufacturing a three-dimensional light emitting appliance is disclosed, said method comprising: providing a first data model of a three-dimensional area; arranging a plurality of spots for light emitting devices on the three-dimensional area of the first data model, wherein the plurality of spots is substantially evenly distributed over at least a part of the three-dimensional area; transforming the first data model of the three-dimensional area comprising the spots into a substantially two-dimensional and flat second data model, wherein the position of the spots on the second data model is derived; manufacturing a printed circuit board in accordance with the second data model and arranging pads of the printed circuit board on the spots of the second data model; equipping the pads of the printed circuit board with light emitting devices; and bringing the printed circuit board into the shape of the three-dimensional area. Further, a three-dimensional light emitting appliance is disclosed.

A computer-implemented method of designing at least a portion of an electronic circuit schematic is described herein. The method comprises receiving requirements for an electronic circuit or at least a portion of an electronic circuit, creating a set of variables and constraints based on the requirements for the electronic circuit, wherein the constraints limit the possible value that may be assigned to the variables, assigning values to the variables using a solver such that the values of the variables satisfy the constraints, and outputting at least a portion of a designed electronic circuit schematic or circuit schematic specification that meets the requirements for the electronic circuit based on the assigned values of the variables.

A simulation system and a method thereof are disclosed. In the simulation system, a system power transmission model, and analog current time-domain model and digital current time-domain model are connected to obtain power noise generated after a supply current is obtained; jitter time-domain information of each interface connection circuit model under the power noise is obtained based on transmission of a clock signal outputted from a phase lock loop, by a simulation program; next, a voltage step response of a voltage measurement point when a clock terminal of each interface connection circuit model receives an ideal signal, is simulated by the simulation program to generate a first voltage time-domain model; a system waveform is generated based on the jitter time-domain information of each interface connection circuit model under the power noise, the first voltage time-domain model and data transmission, thereby obtaining an eye diagram and time-domain jitter distribution.

There is a need for more effective and efficient printed circuit board (PCB) design. This need can be addressed by, for example, solutions for performing automated PCB component estimation. In one example, a method includes identifying a plurality of initial component estimations for the PCB; performing a shadow detection segmentation using the plurality of initial component estimations, a non-direct-lighting image, and one or more direct-lighting images to generate a first set of detected PCB components; performing a super-pixel segmentation using the plurality of initial component estimations and the non-direct-lighting-image to generate a second set of detected PCB components; and generating a bill of materials for the PCB based at least in part on the first set of detected PCB components and the second set of detected PCB components.

A design program for causing a computer to execute a process including: selecting, based on design data of a printed wiring board, a first transmission line and a second transmission line among transmission lines provided in the printed wiring board; adjusting a first wiring length between a first via in the first transmission line and a third via in the first transmission line, a second wiring length between a second via in the second transmission line and a fourth via in the second transmission line, a length of the first via, a length of the second via, a length of the third via, or a length of the fourth via such that a phase of first crosstalk noise generated between the first via and the second via is inverted between the third via and the fourth via; and outputting the design data corrected based on the adjustment in the board.