A method of evaluating sampling sizes for circuit simulation comprises generating a plurality of coverage scenarios based on a defect universe, determining a coverage amount for each of the plurality of coverage scenarios, and associating the plurality of coverage scenarios with a plurality of bins based on the coverage amount for each of the plurality of coverage scenarios. The method further comprises sampling, with a first sampling size, each of the coverage scenarios to determine first sampled coverage scenarios, and determining an error value for each of the plurality of coverage scenarios based on the coverage amount of each of the plurality of coverage scenarios and a coverage amount of a respective one of the first sampled coverage scenarios. Further, the method comprises generating, with a processor and for the first sampling size, a confidence score for each of the plurality of bins based on the error value for each of the plurality of coverage scenarios, and outputting the confidence score for each of the plurality of bins.

A method of evaluating sampling sizes for circuit simulation comprises generating a plurality of coverage scenarios based on a defect universe, determining a coverage amount for each of the plurality of coverage scenarios, and associating the plurality of coverage scenarios with a plurality of bins based on the coverage amount for each of the plurality of coverage scenarios. The method further comprises sampling, with a first sampling size, each of the coverage scenarios to determine first sampled coverage scenarios, and determining an error value for each of the plurality of coverage scenarios based on the coverage amount of each of the plurality of coverage scenarios and a coverage amount of a respective one of the first sampled coverage scenarios. Further, the method comprises generating, with a processor and for the first sampling size, a confidence score for each of the plurality of bins based on the error value for each of the plurality of coverage scenarios, and outputting the confidence score for each of the plurality of bins.

A system and method for adding interface protection to an electronic design using parameters. The electronic design and interface protection scheme are defined as parameters. An interface protection model creates interface protection implementation parameters that describe the implementation details of the interface protection. A hardware description model uses the electronic design parameters and the interface protection implementation parameters to create a hardware description. The interface protection scheme can be a built-in protection scheme, a user defined scheme, a scheme that includes place holders that the user may define later, and a combination of the preceding. The interface protection scheme may contain components to help with the retiming of the description of hardware.

A method of simulating quantum gates includes shifting a Fock basis for the simulation such that the simulation can be performed in a smaller (e.g. truncated) Hilbert dimension space. To shift the Fock basis, non-orthonormalized basis states are first defined. The defined basis states are then orthonormalized to construct orthonormalized shifted Fock basis state. Matrix elements are determined for an operator in the orthonormalized shifted Fock basis and the operator is used to simulate the quantum gate in the shifted Fock basis.

A system for evaluating fault criticality using machine learning includes a first machine learning module that is trained on a subset of a circuit and used for evaluating whether a node in a netlist of the entire circuit is a critical node, and a second machine learning module specialized to minimize classification errors in nodes predicted as benign. A generative adversarial network can be used to generate synthetic test escape data to supplement data used to train the second machine learning module.

A computer system may receive a layout of a data center, the layout of the data center identifying physical locations of a plurality of server racks, electrical distribution feeds, and uninterruptible power supplies. The computer system may receive a fault domain configuration for the datacenter, the fault domain configuration identifying virtual locations of a plurality of logical fault domains for distributing one or more instances so that the instances are stored on independent physical hardware devices within a single availability fault domain. The computer system may determine the configuration for the data center by assigning the plurality of fault domains to a plurality of electrical zones, wherein each electrical zone provides a redundant electrical power supply across the plurality of logical fault domains in an event of a failure of one or more electrical distribution feeds. The computer system may display the configuration for the data center on a display.

A resilient system implementation in a network-on-ship with at least one functional logic unit and at least one duplicated logic unit. A resilient system and method, in accordance with the invention, are disclosed for detecting a fault or an uncorrectable error and isolating the fault. Isolation of the fault prevents further propagation of the fault throughout the system. The resilient system includes isolation logic or an isolation unit that isolates the fault.

Methods, apparatus, systems and articles of manufacture are disclosed to simulate metastability for circuit design verification. An example apparatus includes an input handler to receive circuit design data indicative of a circuit design, a circuit modeler to generate a simulation model based on the circuit design data, a simulator to simulate operation of the circuit design based on the simulation model, a metastability injector to insert metastability logic into the simulation model during the simulation, and a metastability controller to control the metastability logic during the simulation.

Failure mode, effects, and diagnostic analysis (FMEDA) is performed on hardware Intellectual Property (IP) of an electronic system. The analysis includes accessing a library of safety library components, each safety library component containing failure mode characterizations and safety data about a hardware model; and compiling the safety library components and the hardware IP. The compiling includes mapping instances of hardware models in the hardware IP to corresponding safety library components and aggregating the characterizations and safety data of the corresponding components.

A network system can optimize 3D models for 3D printing. A smoothing operation can be performed for a 3D model that comprises a plurality of voxels by identifying exterior voxels of the 3D model. For a first exterior voxel of the 3D model, an exterior surface orientation can be determined and a smoothing operation can be performed based on the determined exterior surface orientation. The smoothing operation can include performing a triangulation operation based on the determined exterior surface orientation of the first exterior voxel. Furthermore, in response to determining that a dimension of a set of voxels is below a threshold limit, one or more voxels can be added to the set of voxels to satisfy the threshold limit.