Examples herein describe techniques for generating dataflow graphs using source code for defining kernels and communication links between those kernels. In one embodiment, the graph is formed using nodes (e.g., kernels) which are communicatively coupled by edges (e.g., the communication links between the kernels). A compiler converts the source code into a bitstream and/or binary code which configures programmable and non-programmable logic in a heterogeneous processing environment of a SoC to execute the graph. The compiler can also consider user-defined constraints when compiling the source code. The constraints can dictate where the kernels and buffers should be placed in the heterogeneous processing environment, performance requirements, data communication routes through the SoC, type of data path, delays, and the like.

A method for generating a technical system model executable on a test unit, wherein the test unit and the executable model are designed for real-time-capable testing of a control unit connected to the test unit, and wherein the executable model is constructed from a plurality of executable submodels communicating with each other, wherein each executable submodel has a separate address space and/or is executed on a separate processor or separate processor core when a test of a control unit connected to the test unit is being run.

One or more processors receive a breakpoint. The breakpoint is paired with a resume point. One or more processors execute a set of machine instructions on a virtual processor model. One or more processors halt execution of the set of machine instructions on the virtual processor model at the breakpoint. One or more processors execute a fragment of a program instruction on a physical processor. The fragment is logically equivalent to the set of machine instructions between the breakpoint and the resume point. One or more processors load a processed result into the virtual processor model. The processed result results from executing the fragment on the physical processor. One or more processors resume the execution of the set of machine instructions on the virtual processor model at the resume point.

Address generators for use in verifying an integrated circuit hardware design for an n-way set associative cache. The address generator is configured to generate, from a reverse hashing algorithm matching the hashing algorithm used by the n-way set associative cache, a list of cache set addresses that comprises one or more addresses of the main memory corresponding to each of one or more target sets of the n-way set associative cache. The address generator receives requests for addresses of main memory from a driver to be used to generate stimuli for testing an instantiation of the integrated circuit hardware design for the n-way set associative cache. In response to receiving a request the address generator provides an address from the list of cache set addresses.

Generating an abstract model of the behavior of a hardware and/or software design. A learning framework learns an unknown regular language that represents the behaviors of the hardware and/or software logic which do not violate a specified property that the abstract model is required to satisfy. The framework receives input data including the specified property, concrete models of the behavior of the hardware and/or software; and an alphabet of all symbols that are allowed to occur in any string that can be defined in the unknown regular language, each symbol representing an event in the hardware and/or software. The framework generates an abstract model of the behavior of the hardware or software design by checking whether a sequence of events in a concrete model satisfies the specified property and outputs the generated abstract model.

The independent claims of this patent signify a concise description of embodiments. Multiple copies of the design or multiple designs are compiled into a single emulation module or prototype FPGA/sub-system to enable multiple concurrent users. The design is executed on the emulator or prototype with the main design clock always running. A debug transactor is attached to each copy of the design which connects to one software debugger per user. The improvement is especially important for long interactive debug sessions which often occur with embedded-software debug use models. This Abstract is not intended to limit the scope of the claims.

An electronic system-level parallel simulation method by means of a multi-core computer system, comprising the parallel evaluation of a plurality of concurrent processes of the simulation on a plurality of cores of the computer system and comprising a sub-method of detection of conflicts of access to a shared memory of a simulated electronic system, the sub-method being implemented by a simulation kernel executed by the computer system and comprises: a step of construction of an oriented graph representative of access to the shared memory by the processes evaluated by the concurrent processes; and a step of detection of loops in the graph; a loop being considered representative of a conflict of access to the shared memory. A computer program product for implementing such a method is provided.

An efficient unreachability analysis tool utilizes toggle coverage report data to automatically generate constraints associated with viable constant signals (e.g., constant inputs, one-time programmable and constant registers) utilized in a circuit design before performing a full unreachability analysis process, thereby improving the functioning of the computer/processor executing the unreachability analysis process by identifying low-activity registers and constraining them before the unreachability analysis process is performed, thereby substantially reducing the number of process steps required to identify dead code (unreachable signal/register targets). Constant inputs are identified using the toggle coverage report and used to generate corresponding constraints, and an initial unreachability analysis process is performed using only toggle coverage properties, then the full unreachability analysis process is performed for all (i.e., line, conditional, state/FSM and toggle) coverage properties using the constant input constraints. Constraints are also generated for one-time programmable and constant registers (OTP/C) before performing the full unreachability analysis process.

Example implementations described herein are directed to resolving issues related to the processor model in the S-PILS (Simulated Processor In the Loop Simulation) system, such as processor model correctness and simulation execution speed, by using the actual Central Processing Unit (CPU) board with silicon CPU instead of the virtual SoC model in the S-PILS.

A method for creating a model of a technical system, is provided, the model being compatible with a simulation device. The simulation device is a simulation device set up for control unit development and the compatible model is executable on the simulation device. The method includes: providing a simulation-device-incompatible model of the technical system; providing a virtual execution environment, wherein the simulation-device-incompatible model of the technical system is executable in the virtual execution environment; and encapsulating the simulation-device-incompatible model of the technical system and the virtual execution environment in a compatible container unit forming the compatible model of the technical system. The incompatible model of the technical system can be addressable via the compatible container unit and the virtual execution environment on simulation device.