For an application having a software portion for implementation in a data processing engine (DPE) array of a device and a hardware portion for implementation in programmable logic (PL) of the device, an implementation flow is performed, using a processor executing a hardware compiler, on the hardware portion based on an interface block solution that maps logical resources used by the software portion to hardware of an interface block coupling the DPE array to the PL. In response to not meeting a design metric during the implementation flow, an interface block constraint is provided from the hardware compiler to a DPE compiler. In response to receiving the interface block constraint, an updated interface block solution is generated, using the processor executing the DPE compiler, and provided from the DPE compiler to the hardware compiler.

A network system can optimize 3D models for 3D printing. A smoothing operation can be performed for a 3D model that comprises a plurality of voxels by identifying exterior voxels of the 3D model. For a first exterior voxel of the 3D model, an exterior surface orientation can be determined and a smoothing operation can be performed based on the determined exterior surface orientation. The smoothing operation can include performing a triangulation operation based on the determined exterior surface orientation of the first exterior voxel. Furthermore, in response to determining that a dimension of a set of voxels is below a threshold limit, one or more voxels can be added to the set of voxels to satisfy the threshold limit.

A system and method of verifying hardware that includes software configured to control its operation, the method comprising providing an abstracted version of hardware to be tested; verifying the functionality of the hardware; writing test bench software using physical-layer routines; drafting hybrid verification intellectual property modules, wherein the hybrid verification intellectual property modules comprise both synthesizable and non-synthesizable code and are configured to stimulate the abstracted hardware and to test software anticipated to be used in connection therewith; and creating network-level routines that can be passed to physical-layer routines as part of a hardware verification process.

Disclosed are methods, systems, and articles of manufacture for probing a multi-fabric electronic design that spans across multiple design fabrics. These techniques identify a single layout editor, a first electronic design in a first design fabric, and a second electronic design in a second design fabric. An input for probing a circuit component in the first electronic design may further be identified at a user interface of a computing system. The circuit component being probed is connected to an instance of the second electronic design. In response to the input, one or more co-design modules render a representation of the first layout with emphasized circuit components in the first design fabric and the second design fabric, wherein the one or more co-design modules are stored at least partially in memory of and function in conjunction with at least one microprocessor of a computing system.

A 3D model system is configured to validate and optimize for 3D printing an unprocessed 3D model described by an input data file. The 3D model system is configured to detect printability issues associated with the unprocessed 3D model and automatically address these issues. Such issues can include boundary edges, non-manifold geometries, structural deficiencies, etc. Upon resolving these issues, the 3D model can be optimized for 3D printing. Optimizations can include hollowing to reduce printing cost and exterior surface smoothing. The resulting validated and optimized 3D model can be converted into an output data file which can be an input to a 3D printer or a 3D printing service for printing the object depicted by the 3D model. The 3D model system can operate as a network or cloud-based service. Users are able to interact with the 3D model system using a series of web-based user interfaces.

Methods, systems and apparatuses may provide for technology that applies a functional safety test stimulus to a hardware level simulator, automatically compiles an output of the hardware level simulator into a software test library (STL), and iteratively verifies that the diagnostic coverage of the STL file approximates the diagnostic coverage of the functional safety test stimulus.

The present disclosure is directed to methods and systems for automated design of a system of hardware and software. In an exemplary embodiment, such a method comprises constructing, by a hardware processor, a model of use based on an architecture description of the system, constructing, by the hardware processor, threat model based on a threat description indicating known threats to the system, determining use of the system based on a comparison between the model of use and the threat model and selecting a configuration for realizing the system based on a result of the comparison.

A method for controlling the course of a signal flow-based computer program having interconnected software components and at least one DF loop. The following method steps are performed: a) identifying the at least one DF loop and the DF components, each DF component instantaneously imaging at least one DF input signal present at at least one component input onto at least one output signal present at at least one component output, b) determining the maximum possible change of the values of the DF input signals for each unit of time from at least one property of the respective DF input signal, c) activating a delay element in front of the component input where a DF input signal is present whose value has the smallest maximum possible change, and d) running the computer program in accordance with the connection of the software components ascertained in steps a) to c).

For an application having a software portion for implementation in a data processing engine (DPE) array of a device and a hardware portion for implementation in programmable logic (PL) of the device, an implementation flow is performed, using a processor executing a hardware compiler, on the hardware portion based on an interface block solution that maps logical resources used by the software portion to hardware of an interface block coupling the DPE array to the PL. In response to not meeting a design metric during the implementation flow, an interface block constraint is provided from the hardware compiler to a DPE compiler. In response to receiving the interface block constraint, an updated interface block solution is generated, using the processor executing the DPE compiler, and provided from the DPE compiler to the hardware compiler.

Address generators for use in verifying an integrated circuit hardware design for an n-way set associative cache. The address generator is configured to generate, from a reverse hashing algorithm matching the hashing algorithm used by the n-way set associative cache, a list of cache set addresses that comprises one or more addresses of the main memory corresponding to each of one or more target sets of the n-way set associative cache. The address generator receives requests for addresses of main memory from a driver to be used to generate stimuli for testing an instantiation of the integrated circuit hardware design for the n-way set associative cache. In response to receiving a request the address generator provides an address from the list of cache set addresses.