The present disclosure relates to systems, methods, and products for adaptive design and optimization using a physics-informed neural network (PINN). The system includes a non-transitory memory and a processor. The processor executes instructions to cause the system to: input collocation points and design parameters into the PINN to obtain an output; calculate a loss function based on a set of governing equations and the output; determine whether the PINN is convergent based on the calculated loss function; in response to the PINN being convergent, export the PINN; and in response to the PINN not being convergent: determine whether to resample the collocation points; determine an optimum number of collocation points; determine a set of optimal network parameters for adjusting the PINN; and input the collocation points and the set of optimal network parameters to the PINN for a next iteration.

A system for determining a health state of a component includes a processor and a non-transitory computer-readable storage medium that stores a plurality of computer-executable instructions thereon. The processor, in response to executing the plurality of computer-readable instructions, may be configured to perform one or more steps. The steps may include obtaining, from a first data source, usage data for the component; obtaining, from a second data source, a condition indicator for the component; running a usage model to produce usage parameters for the component based on the usage data; running a damage model to produce a damage estimate for the component based on the usage parameters; and running a prediction model to produce a health state estimate of the component based on the damage estimate and the condition indicator.

Methods and systems for performing fault injection testing on an integrated circuit hardware design. The methods include: (a) receiving a raw fault node list identifying one or more fault nodes of the hardware design; (b) receiving information indicating a grouping of the fault nodes in the raw fault node list into a plurality of fault node groups, each fault node group comprising fault nodes that have a same effect on a failure mode of the hardware design; (c) generating a final fault node list based on the fault node groups; (d) selecting a set of fault injection parameters from the final fault node list, the set of fault injection parameters identifying at least one fault node in the final fault node list to fault; (e) performing a fault injection test on the hardware design by causing a fault to be injected into a simulation of the hardware design based on the selected set of fault injection parameters; (f) determining a result of the fault injection test; (g) storing the result of the fault injection test; and repeating (d) to (g) at least once.

An embodiment of an integrated circuit may comprise a management controller and circuitry communicatively coupled to the management controller, the circuitry to dynamically determine a performance measurement for each of two or more circuit blocks based at least in part on the physical design layout of the two or more circuit blocks, and report a schedule recommendation to an operating system scheduler based at least in part on the determined performance measurements. Other embodiments are disclosed and claimed.

Various embodiments provide for failure mode analysis of a circuit design, which can be used as part of electronic design automation (EDA). In particular, some embodiments provide for failure mode analysis of a circuit design by determining a set of functional primitives of a circuit design component (e.g., cell at gate level) that contribute to a root cause logic for a specific failure mode.

A method for identifying a critical error of a worm gear machine, step 1: obtaining an actual forward kinematic model T.sub.27.sup.a and an ideal forward kinematic model T.sub.27.sup.i from a coordinate system of a worm gear hob to a coordinate system of a worm gear, thereby establishing a geometric error-pose error model of the worm gear machine; step 2: regarding the geometric error-pose error model of the worm gear machine as a multi-input multi-output (MIMO) nonlinear system, and solving, by taking the geometric error of each motion axis of the worm gear machine as an input feature X, and a pose error between the worm gear hob and the worm gear as an output variable Y, an importance coefficient of each input feature with a random forest algorithm; and step 3: determining a critical error affecting a machining accuracy of the worm gear machine.

According to examples, a processor may dilate a first digital model of a first 3D part a predefined amount and a second digital model of a second 3D part the predefined amount, in which the first 3D part and the second 3D part are to be fabricated together in an assembly to have a functional relationship with respect to each other, and in which the first digital model and the second digital model are spaced from each other in a manner that corresponds to a spacing of the first 3D part and the second 3D part in the assembly. The processor may determine a spatial relationship between the dilated first digital model and the dilated second digital model and may determine, based on the determined spatial relationship, whether the assembly of the first 3D part and the second 3D part is predicted to function properly when the assembly is fabricated.

A JTAG-based burning device, comprising controllable switches provided between a TDI end of a JTAG host (1) and a first chip and between every two adjacent chips, and further comprising a main controllable switch module (2) provided between each chip and a TDO end of the JTAG host (1). According to a received burning instruction, the JTAG host (1) can control an input end of a corresponding controllable switch to be connected to a corresponding output end thereof, and also control an output end of the main controllable switch module (2) to be connected to a corresponding input end thereof. Hence, the device merely needs to build a circuit to automatically adjust a JTAG link by controlling the connection relationship between the input end and the output end of the corresponding switch, achieving burning of the firmware of different chips or a combination of chips, without manual adjustment, thereby improving the test efficiency, and simplifying a circuit structure.

A computer-implemented method of generating a visual representation of items comprising selecting a pair of items m and n comprising parameters representing a property, selecting a pair of parameters p and q, being a.sub.mp the parameter p of item m, b.sub.mq the parameter q of item m, a.sub.np the parameter p of item n, and b.sub.nq the parameter q of item n, calculating a pair of weights w.sub.p and w.sub.q based on a.sub.mp, b.sub.mq, a.sub.np and b.sub.nq, and based on a.sub.mp, b.sub.mq, a.sub.np and b.sub.nq, storing, the pair of weights, determining a first vertex item comprising the greatest value for the parameter p, a second vertex item comprising the greatest value for the parameter q, and a third vertex comprising the greatest value for a parameter r, generating a plurality of points based on stored and determined values, and displaying a geometric shape comprising the plurality of points

To increase the efficiency of electronic design automation, a register transfer level debug application client entity requests, from a register transfer level source navigator server, combined register transfer level and hardware aspect metadata including debug instrumentation. The register transfer level debug application client entity receives, from the register transfer level source navigator server, the combined register transfer level and hardware aspect metadata including the debug instrumentation. The register transfer level debug application client entity transforms the combined register transfer level and hardware aspect metadata including the debug instrumentation. The register transfer level debug application client entity renders the transformed combined register transfer level and hardware aspect metadata including the debug instrumentation.