Patent classifications
G06F2119/06
Method and System for Predicting Specific Energy of Cutter Head of Tunnel Boring Machine
A method for predicting a specific energy of a cutter head of a tunnel boring machine includes obtaining a parameter of the tunnel boring machine to be measured configured to influence the specific energy of the cutter head to be measured, and inputting the obtained parameter of the tunnel boring machine to be measured into a model for predicting the specific energy of an apparatus to obtain a total predicted specific energy value of the cutter head and a proportion of each component of the total predicted specific energy value. The method comprehensively considers various influence factors, and outputs a proportion and a change of each component in the specific energy of the cutter head along with the construction process, thereby providing a foundation for optimal allocation of the specific energy of the cutter head of the tunnel boring machine.
Floorplan of a design for an integrated circuit
A computer-implemented method for comparing a first version of a floorplan of a design for an integrated circuit with a second version. The method comprises (i) generating a timing information for each net in the second version by determining whether timing information is available for the net in the first version; (ii) in case no timing information is available in the first version, generating the timing information for the second version by calculating a spatial distance and timing information between two points of the net using wire length differences between the first version and the second version; (iii) otherwise, generating the timing information for the second version by calculating a spatial distance and timing information between two points of the net using a wire reach table to obtain a wire delay.
CIRCUIT UNIT HAVING ADJUSTABLE DRIVING STRENGTH CAPABILITY IN CHIP AND METHOD THEREOF
A circuit unit in a chip includes a main circuit portion and a configurable portion. The configurable portion includes an output stage, a plurality of configurable stages, and a configurable metal layer. The configurable stages are configured to be connected in sequence to the output stage. The configurable metal layer is connected to the output stage. The main circuit portion is configured to be adjacent to and connected to the output stage of the configurable portion. A driving strength of the circuit unit is determined based on a connection relationship between each of the plurality of configurable stages and the configurable metal layer.
CENTRALIZED AI-BASED TOPOLOGY PROCESS FOR DIFFERENTIAL PROTECTION OF A POWER SUBSTATION
Systems, methods, and computer-readable media are disclosed. An example method may include receiving a single-line drawing (SLD) of a power substation, the SLD including one or more components, the one or more components including at least one of: a current transformer (CT), a circuit breaker (CB), an isolator, a feeder, and a busbar. The example method may also include analyzing, using an artificial intelligence (AI) system, connection paths associated with the one or more components in the SLD. The example method may also include receiving real-time data relating to a status of the CB and a status of the isolator. The example method may also include providing, based on analyzing the connection paths, and the real-time data relating to the status of the CB and the status of the isolator, an indication of topology information associated with the power substation, the topology information including at least one of: an indication that the CT is a checkzone CT, an indication that the CT is a deadzone CT, an indication of a zone associated with the CT or the CB, or an indication that a zone is unprotectable.
Systems and Methods for Providing A Dynamic High Voltage Circuit Design Workflow
Systems and methods are provided for designing an integrated circuit device. In one example, a method for designing an integrated circuit device may include the operations of: receiving a schematic diagram of the integrated circuit device; generating, by a simulation program, a first transient simulation of the integrated circuit device based on the schematic diagram; determining from the first transient simulation of the integrated circuit device a plurality of maximum voltage change values between conductor networks (nets) within the schematic diagram of the integrated circuit device; storing the plurality of maximum voltage change values for the schematic diagram of the integrated circuit device in a computer readable medium; and utilizing, by a layout program, the stored plurality of maximum voltage change values to generate a layout design for the integrated circuit device according to one or more high voltage design constraints. In embodiments, the plurality of maximum voltage change values are stored in the form of a matrix in an extensible markup language (XML) file.
METHODS AND SYSTEMS TO DETERMINE PARASITICS FOR SEMICONDUCTOR OR FLAT PANEL DISPLAY FABRICATION
Some embodiments provide a method for calculating parasitic parameters for a pattern to be manufactured on an integrated circuit (IC) substrate. The method receives a definition of a wire structure as input. The method rasterizes the wire structure (e.g., produces pixel-based definition of the wire structure) to produce several images. Before rasterizing the wire structure, the method in some embodiments decomposes the wire structure into several components (e.g., several wires, wire segments or wire structure portions), which it then individually rasterizes. The method then uses the images as inputs to a neural network, which then calculates parasitic parameters associated with the wire structure. In some embodiments, the parasitic parameters include unwanted parasitic capacitance effects exerted on the wire structure. Conjunctively, or alternatively, these parameters include unwanted parasitic resistance and/or inductance effects on the wire structure.
System and method for characterization of air leakage in building using data from communicating thermostats and/or interval meters
Systems and methods for characterization of retrofit opportunities are described. Some embodiments are directed to methods for determining the air leakage rate of a building, and accordingly, for determining suitability of sealing of air leaks to improve the energy efficiency of a building. The methods may comprise computing, using at least one computing device disposed remote from a building and based at least in part on heating, ventilation and air conditioning (HVAC) runtime data associated with the building, one or more thermal characteristics of the building. The HVAC runtime data may be computed based on data received from a thermostat or a meter, such as an electric or a gas meter. To isolate the impact of air leakage, subsets of the HVAC runtime data at time intervals selected to have substantially the same conditions, but different wind speeds, may be computed.
TRACTION POWER SIMULATION
Systems and methods are provided for simulating traction power and control in transportation systems under design conditions and/or utilizing real-time data.
SYSTEMS AND METHODS FOR MODELING VIA DEFECT
A method includes acquiring a design layout of a standard cell, extracting feature information of one or more vias in the standard cell from the design layout, performing a circuit simulation to obtain first simulation outputs of the standard cell for input patterns by applying a first abnormal resistance value as a parasitic resistance value of a first via among the one or more vias, the first abnormal resistance value being different from a nominal parasitic resistance value of the first via, determining whether the first simulation outputs match corresponding expected outputs of the standard cell for the input patterns, and in response to one or more simulation outputs among the first simulation outputs not matching the corresponding expected outputs, recording one or more defect types for the first via having the first abnormal resistance value along with corresponding input patterns and corresponding simulation outputs.
DIAGNOSIS OF INCONSISTENT CONSTRAINTS IN A POWER INTENT FOR AN INTEGRATED CIRCUIT DESIGN
A power intent may be loaded on an integrated circuit (IC) design, where the power intent may be represented by a set of constraints. A logic network may be constructed based on the set of constraints and a rule check which is desired to be performed on the power intent. In response to a failure of the rule check, one or more refutation proofs may be created based on the logic network. A subset of the set of constraints may be identified based on the one or more refutation proofs, where the subset of the set of constraints may include an inconsistency which caused the rule check to fail.