Patent classifications
G06F2119/06
NOISE SIMULATION SYSTEM
The disclosure provides a system to simulate a simulated noise on the power zone block of a substrate. The system comprises a signal trace and a signal generating circuit. The signal trace is disposed adjacent to the power zone block. The signal generating circuit is electrically coupled to the signal trace, configured to transmit an alternating current signal over the signal trace. The alternating current signal transmitted over the signal trace is configured to induce a simulated noise on the power zone block, and a waveform of the simulated noise is determined by a frequency of the alternating current signal.
CIRCUIT SIMULATION METHOD AND DEVICE
A circuit simulation method includes the following: a key character string corresponding to at least one target power supply node is determined; a node identifier corresponding to the at least one target power supply node is searched out from a first netlist corresponding to the to-be-simulated circuit according to the key character string; and a power supply voltage file corresponding to the at least one target power supply node is generated according to the searched-out node identifier, and the to-be-simulated circuit is simulated according to the power supply voltage file. The circuit simulation method and the device provided by the embodiments of the present disclosure may rapidly generate the power supply voltage file corresponding to the target power supply node, which can not only effectively improve the circuit simulation efficiency, but also ensure the accuracy of a simulation result.
Time-based power analysis
Systems, machine readable media and methods are described for analyzing one or more physical systems using techniques that recognize patterns in underlying data and use the patterns to efficiently compute outputs using the patterns to reduce computations. The physical systems can be simulated with an estimation (e.g., an estimated power versus time waveform) that can be efficiently computed and then the estimation can be analyzed to detect patterns in the data. The detected patterns can each be analyzed with, in one embodiment, higher accuracy than the estimation to provide data that can be combined across multiple instances of each pattern to provide a higher accuracy evaluation of the system with a lower computational overhead.
Computer-implemented method for simulation of an electrical circuit
A computer-implemented method for simulation of an electrical circuit with circuit components by at least one computing unit includes mapping a coupling of the substate representations in a coupling equation system for exchange of calculated coupling variables between the subcircuits. The method also includes calculating, in an evaluation step, at least one stability parameter on a basis of the coupling equation system, and deciding, in a selection step and depending on the at least one calculated stability parameter, whether the current separation of the electrical circuit into subcircuits will be used as the basis of the simulation. The method further includes performing, after a successful selection, the simulation of the electrical circuit by calculating the substate space representations on the at least one computing unit.
METHOD FOR MODELING POWER CONSUMPTION OF AN INTEGRATED CIRCUIT AND POWER CONSUMPTION MODELING SYSTEM PERFORMING THE SAME
Example embodiments relate to a method for modeling power consumption of an integrated circuit, the method may comprise, determining, by the processor, a hierarchy structure regarding a gating level according to a clock flow of a plurality of clock gating cells included in the integrated circuit, determining, by the processor, a first clock gating domain corresponding to a first clock gating cell and a second clock gating domain corresponding to a second clock gating cell located in a lower level of the hierarchy of the first clock gating cell based on the hierarchy structure, calculating, by the processor, power consumption of the second clock gating domain based on a first logic level of a first clock gating enable signal applied to the first clock gating cell, and modeling, by the processor, power consumption of the integrated circuit based on the power consumption of the second clock gating domain.
Method, computer readable medium and system for automated design of controllable oscillator
An method, a computer readable medium and a system for an automated design of a controllable oscillator are provided, wherein the method includes: receiving a set of input data through an automated design procedure, wherein the set of input data includes an initial circuit description file and a criteria file, and the initial circuit description file records initial values of parameters of one or more components within the controllable oscillator; performing simulation according to the set of input data through the automated design procedure to generate a simulation result; and selectively modifying at least one parameter within the parameters of the one or more components according to the simulation result through the automated design procedure. In addition, in the process of modifying the at least one parameter, connection relationships of all components within the controllable oscillator are unchanged.
INTEGRATED CIRCUIT AND METHOD OF FORMING THE SAME
An integrated circuit includes a first cell, a second cell, a buffer zone and a first power rail. The first cell includes a first set of fins extending in a first direction. Each fin of the first set of fins corresponds to a transistor of a first set of transistors. The second cell includes a second set of fins extending in the first direction. Each fin of the second set of fins corresponds to a transistor of a second set of transistors. The second set of fins is separated from the first set of fins in a second direction. The buffer zone is between the first cell and the second cell. The first power rail extends in the first direction, and overlaps at least the buffer zone. The first power rail is in a first metal layer, and is configured to supply a first voltage.
Graphical user interface for controlling a solar ray mapping
Systems, methods, and computer-readable media are described herein to model divergent beam ray paths between locations on a roof (e.g., of a structure) and modeled locations of the sun at different times of the day and different days during a week, month, year, or another time period. A graphical user interface allows for visualization of the modeled ray paths and graphical manipulation of the resolution and parameters of the modeling process.
STATIC VOLTAGE DROP (SIR) VIOLATION PREDICTION SYSTEMS AND METHODS
Systems and methods are provided for predicting static voltage (SIR) drop violations in a clock-tree synthesis (CTS) layout before routing is performed on the CTS layout. A static voltage (SIR) drop violation prediction system includes SIR drop violation prediction circuitry. The SIR drop violation prediction circuitry receives CTS data associated with a CTS layout. The SIR drop violation prediction circuitry inspects the CTS layout data associated with the CTS layout, and the CTS layout data may include data associated with a plurality of regions of the CTS layout, which may be inspected on a region-by-region basis. The SIR drop violation prediction circuitry predicts whether one or more SIR drop violations would be present in the CTS layout due to a subsequent routing of the CTS layout.
Method for determining an electrical model of a string of photovoltaic modules, diagnostic method and device associated therewith
A method for determining an electrical model of a string of photovoltaic modules from a characteristic I(V) of the string includes detecting a first linear zone and a second linear zone of the characteristic I(V); initialising the parameters of a non-by-pass electrical model corresponding to a first operating condition, called a non-by-pass condition; optimising the parameters of the non-by-pass electrical model from a reference characteristic I(V.sub.ref) equal to I(V), determining the parameters of the electrical model corresponding to a second operating condition, called a by-pass condition, in order to obtain a by-pass electrical model from the characteristic determining, from the characteristic I(V) the best model among the non-by-pass model and the by-pass model.