Apparatus and associated methods relate to determining a fit-quality metric for a mask/face combination based upon a calculated dead-space volume between a virtual mask and a virtual face virtually aligned so as to create an integrity seal circumscribing a mouth and nose region. In an illustrative embodiment, an interactive virtual fitting system may receive a three-dimensional (3D) virtual face associated with a person. The system may retrieve 3D models of various respirators selected by user determined criteria. The system may then compute a fit-quality metric for each of the retrieved 3D models. The potential wearer may then be presented with the metrics for review. The potential wearer may select a respirator based upon these computed metrics. A virtual fitting of many respirators may advantageously reduce the time needed for selecting a properly fitting respirator while simultaneously ensuring that the selected respirator may be comfortable and well fitting.

Methods and systems for verifying a property of an integrated circuit hardware design. The method includes formally verifying, using a formal verification tool, that the property is true for the hardware design under a constraint that an instantiation of the hardware design transitions to a quiescent state at a symbolic time.

Embodiments include herein are directed towards a method for use in an electronic design environment is provided. Embodiments may include receiving a printed circuit board schematic and one or more electronic circuits. Embodiments may further include automatically generating, one or more circuit templates based upon, at least in part, the printed circuit board schematic and one or more electronic circuits. The one or more circuit templates may be stored at an electronic design database. Embodiments may also include receiving a current printed circuit board schematic and automatically determining whether a subcircuit of the current printed circuit board schematic is an exact or approximate match with the one or more circuit templates.

An analog circuit netlist translation system is disclosed. The analog circuit netlist translation system comprises a model translation module configured to receive an analog circuit netlist; and transform the analog circuit netlist into a digital model. In some embodiments, the digital model comprises a set of zero-delay loops. The analog circuit netlist translation system further comprises a translation methodology module configured to determine a set of closed loop values respectively associated with the set of zero-delay loops, in order to eliminate the set of zero-delay loops within the digital model. In some embodiments, the set of closed loop values are determined by the translation methodology module in a single timeslot.

In various embodiments, a style comparison application generates visualization(s) of geometric style gradient(s). The style comparison application generates a first set of style signals based on a first 3D CAD object and generates a second set of style signals based on a second 3D CAD object. Based on the first and second sets of style signals, the style comparison application computes a different partial derivative of a style comparison metric for each position included in a set of positions associated with the first 3D CAD object to generate a geometric style gradient. The style comparison application generates a graphical element based on at least one of the direction or the magnitude of a vector in the geometric style gradient and positions the graphical element relative to a graphical representation of the first 3D CAD object within a graphical user interface to generate a visualization of the geometric style gradient.

Methods and systems for verifying a hardware design for an integrated circuit that implements a function that is polynomial of degree k in a sub-function p over a set of values of p, k being an integer greater than or equal to one. The methods include: verifying that an instantiation of the hardware design correctly evaluates the sub-function p; formally verifying that an instantiation of the hardware design implements a function that is polynomial of degree k in p by formally verifying that, for all values of p in the set of values of p, an instantiation of the hardware design has a constant k.sup.th difference; and verifying that an instantiation of the hardware design generates an expected output in response to each of at least e different values of p in the set of values of p, wherein e is equal to k when a value of the k.sup.th difference is predetermined and e is equal to k+1 when the value of the k.sup.th difference is not predetermined.

A system and method for characterizing a memory instance. Characterizing a memory instance includes obtaining a memory instance comprising a plurality of leaf cells. Each of the plurality of leaf cells comprises components. First channel connected components from the components within each of the plurality of leaf cells are determined, and a first super leaf cell is generated by combining a first two or more leaf cells of the plurality of leaf cells based on the first channel connected components. Further, an updated memory instance is generated based on the first super leaf cell, and a timing model is determined for the updated memory instance.

Aspects of the invention include systems and methods for to detecting security vulnerabilities using modeled attribute propagation. A non-limited example of a computer-implemented method includes generating a model of a device under test, the model comprising a data path similar to the device under test and an attribute network. The method further includes detecting protected data that is introduced into the model and marking the protected data with an attribute. An end point of the marked protected data is detected along the data path. In response to the end point being indicative of a vulnerability, an alert is issued.

The present disclosure provides a method and a system for determining the equivalence of the DRM data set and the DRC data set. The system retrieves a DRM data set and a DRC data set, and transforms the DRM data set and the DRC data set into a first data structure node and a second data structure node respectively. The system determines whether the first data structure node and the second data structure node are equivalent according to a data structure node comparison model.

Techniques and systems for solving Boolean satisfiability (SAT) problems are described. Some embodiments solve SAT problems using efficient construction of truth tables. Some embodiments can improve performance of SAT solvers by using truth tables instead of incurring the overhead of Conjunctive Normal Form (CNF) conversion.