A method for designing a system on a target device includes performing register retiming on an original design for the system to generate a retimed design. The retimed design is verified to determine whether it is structurally correct by performing a plurality of iterations of register retiming on the retimed design, wherein each iteration accounts for the retiming of registers in the system driven by a different clock.

Disclosed herein is a fundamental modeling and control method in dynamic energy conversion and transfers in complex energy systems with multiple energy sources, fuel and electric. The multi-layered modeling enables efficient and stable operation through optimized coordination of engines and electric part of a hybrid turbo-electric distribution system (TeDP). A provable coordination of power and rate of change of power interactions between the components is done at the higher-system level. Advanced nonlinear control of components is disclosed to ensure that components meet power/rate of change of power commands given by the higher level. This method is used to demonstrate, for the first time, how rotor stall and surge instabilities in engines can be eliminated by controlling the electric generators and/or storage.

A method and apparatus for forcing equivalent outputs at start-up for replicated sequential circuits is disclosed. An integrated circuit (IC) includes first and second clocked logic circuits each coupled to receive a clock signal common to both, and each configured to produce equivalent logical outputs based on a common set of logic inputs. The IC further includes an equivalence circuit coupled to the outputs of each of the first and second clocked logic circuits. During a system start-up (e.g., power on) and before the clock signal has been applied, the equivalence circuit may detect if the outputs of the to first and second clocked logic circuits originally come up in different states. Responsive to determining that the outputs of the first and second clocked logic circuits are different, the equivalence circuit may cause the outputs to be forced to the same logical state.

A method for designing a system on a target device includes performing register retiming on an original design for the system to generate a retimed design. The retimed design is verified to determine whether it is structurally correct by performing a plurality of iterations of register retiming on the retimed design, wherein each iteration accounts for the retiming of registers in the system driven by a different clock.

A method, computer program, and apparatus are described for finding the logical equivalence between register transfer level (RTL) wires and post synthesis nets in a netlist. In some example embodiments, the method includes minimizing nets in a netlist and matching each RTL wire to a netlist net. In some example embodiments, the method also includes determining if an RTL wire is logically equivalent to a netlist net. In some example embodiments, the method also includes determining a new candidate for a net if the RTL wire and associated netlist net are not logically equivalent.

A power inductor evaluation apparatus includes a storage unit and a determination unit. The storage unit stores the simulation model of a DC-DC converter. The simulation model includes the equivalent circuit model of a power inductor, including a DC superimposition characteristics slope and a saturation current Isat as parameters. The determination unit inputs the DC superimposition characteristics slope and the saturation current Isat into the simulation model of the DC-DC converter and performs simulation, and determines whether or not the power inductor having the DC superimposition characteristics slope and the saturation current Isat is usable on the basis of whether or not the simulation results satisfy design requirements (e.g, a permissible ripple voltage and a peak current).

An equivalent circuit is capable of, while having a simple configuration, accurately expressing a superposition characteristic and having excellent practicality and workability. A current sensor and a voltage source are connected in series between external terminals of an equivalent circuit. A reference state element having an impedance forms a closed loop with a current source. A current flowing through the equivalent circuit and detected by the current sensor is reproduced by the current source and then applied to the reference state element, so that a potential difference is generated across the reference state element. A voltage obtained by multiplying the potential difference by a correction coefficient is outputted by the voltage source. By setting the correction coefficient to be dependent on the current or an inter-terminal voltage, the impedance represented by the equivalent circuit can be reproduced as a characteristic dependent on the current I or the inter-terminal voltage.

A hardware design for a main data transformation component is verified. The main data transformation component is representable as a hierarchical set of data transformation components which includes (i) leaf data transformation components which do not have children, and (ii) parent data transformation components which comprise one or more child data transformation components. For each of the leaf data transformation components, it is verified that an instantiation of the hardware design generates an expected output transaction. For each of the parent data transformation components, it is formally verified that an instantiation of an abstracted hardware design generates an expected output transaction in response to each of test input transactions. The abstracted hardware design represents each of the child data transformation components of the parent data transformation component with a corresponding abstracted component that for a specific input transaction to the child data transformation component produces a specific output transaction with a causal deterministic relationship to the specific input transaction.

A method, computer program, and apparatus are described for finding the logical equivalence between register transfer level (RTL) wires and post synthesis nets in a netlist. In some example embodiments, the method includes minimizing nets in a netlist and matching each RTL wire to a netlist net. In some example embodiments, the method also includes determining if an RTL wire is logically equivalent to a netlist net. In some example embodiments, the method also includes determining a new candidate for a net if the RTL wire and associated netlist net are not logically equivalent.

Method and apparatus for circuit simulation, comprising: partitioning circuit into a first simulation circuit and a second simulation circuit; generating equivalent circuit of first simulation circuit at present simulation time-point based on port current/port voltage of simulation time-points prior to present simulation time-point, a pre-obtained port voltage of the first simulation circuit under port open-circuit condition/port current of the first simulation circuit under port short-circuit condition, and a pre-obtained impulse-response of the first simulation circuit; simulating circuit consisting of the equivalent circuit and the second simulation circuit based on a preset algorithm to obtain unknowns in the second simulation circuit; and obtaining unknowns in the first simulation circuit based on port current/port voltage. Comparing with prior art, this invention reduces circuit scale by equivalencing linear portion of circuit, namely, the first simulation circuit. Thereby computation amount in simulation process is reduced to meet requirements for real-time simulation.