Pattern centric process control is disclosed. A layout of a semiconductor chip is decomposed into a plurality of intended circuit layout patterns. For the plurality of intended circuit layout patterns, a corresponding plurality of sets of fabrication risk assessments corresponding to respective ones of a plurality of sources is determined. Determining a set of fabrication risk assessments for an intended circuit layout pattern comprises determining fabrication risk assessments based at least in part on: simulation of the intended circuit layout pattern, statistical analysis of the intended circuit layout pattern, and evaluation of empirical data associated with a printed circuit layout pattern. A scoring formula is applied based at least in part on the sets of fabrication risk assessments to obtain a plurality of overall fabrication risk assessments for respective ones of the plurality of intended circuit layout patterns. The plurality of intended circuit layout patterns is ranked based on their fabrication risk assessments, the corresponding overall fabrication risk assessments, or both. At least a portion of ranking information is outputted to facilitate influence or control over the semiconductor fabrication process.

Provided are systems and methods that can extract part data from a PLM database and suggest changes to the manufacturing of the part. In one example, the method may include querying a database for a plurality of values of a part to be manufactured from a plurality of fields of computer-aided design (CAD) file stored in the database, mapping the plurality of fields of the CAD file to a plurality of corresponding fields of a host platform based on a type of the database, extracting the plurality of values from the CAD file and transferring the plurality of values to the mapped plurality of corresponding fields of the host platform, determining changes to one or more manufacturing attributes of the part to be manufactured based on the transferred plurality of values, and outputting the changes to a display.

A method includes receiving a netlist for a chip including a bus and determining, by one or more processors and based on the netlist, a first routing topology for the bus and through a routing region of the chip by comparing a demand of the bus to a capacity of a plurality of cells of the routing region. The method also includes generating a layout for the chip based on the first routing topology.

An integrated circuit includes a middle active-region structure between a group-one active-region structure and a group-two active-region structure. The integrated circuit also includes a main circuit, a group-one circuit, and a group-two circuit. The main circuit includes at least one boundary gate-conductor intersecting the middle active-region structure. The group-one circuit includes a group-one isolation structure separating the group-one active-region structure into a first part in the group-one circuit and a second part in a first adjacent circuit. The group-two circuit includes a group-two isolation structure separating the group-two active-region structure into a first part in the group-two circuit and a second part in a second adjacent circuit.

A method of generating a customized headgear that includes a plurality of physical features and being usable with a mask component that supplies a flow of breathing gas to the patient's airways. The method includes receiving one or more parameters pertaining to the patient's head, subjecting at least some of the parameters to one or more algorithms to determine at least one of a length of a physical feature of the plurality of physical features and an angle between a pair of physical features of the plurality of physical features, generating an outline of at least a portion of a body which, when formed, is usable to assemble therefrom at least a portion of the headgear, and outputting a pattern usable to enable the formation of the at least portion of the body from at least a first sheet of at least a first material.

Systems and methods presented herein provide a plugin to REVIT or a similar program that allows for utilizing nested families for related parts and assemblies. Assembly families can include an inheritance tree where an instance of a host family implements child and sub-child families. The child and sub-child families can inherit parameters from the host family. To manage parameter values associated with the nested structure, the plugin can provide a custom dialog that acts as a middle layer between the user and the parameter settings of the computer-aided design program. The custom dialog can associate user selections with permissible values for parameters related to the host family.

A design method of a dummy pattern layout including the following steps is provided. An integrated circuit layout design including resistor elements is obtained via a computer. The locations of dummy conductive structures are configured, wherein the dummy conductive structures are aligned with the resistor elements. The locations of dummy support patterns are configured, wherein each of the dummy support patterns is configured between two adjacent dummy conductive structures, and each of the dummy conductive structures is equidistant from the dummy support patterns on both sides.

A method for calibrating a process model and training an inverse process model of a patterning process. The training method includes obtaining a first patterning device pattern from simulation of an inverse lithographic process that predicts a patterning device pattern based on a wafer target layout, receiving wafer data corresponding to a wafer exposed using the first patterning device pattern, and training an inverse process model configured to predict a second patterning device pattern using the wafer data related to the exposed wafer and the first patterning device pattern.

A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a first conductive pattern disposed within a first region from a top view perspective and extending along a first direction, a first phase shift circuit disposed within the first region, a first transmission circuit disposed within a second region from the top view perspective, and a first gate conductor extending from the first region to the second region along a second direction perpendicular to the first direction. The first phase shift circuit and the first transmission circuit are electrically connected with the first conductive pattern through the first gate conductor.

A method of compensating for sintering warpage due to powder spreading density variations in binder jetting additive manufacturing, including receiving an initial design file defining an object geometry, representing the object geometry as a part mesh and filling the mesh with a grid of voxels to create a voxel grid, each voxel having at least one shrinkage coefficient. For each voxel, determining a distortion factor caused by a powder density variation induced during a powder spreading process and adjusting the at shrinkage coefficient of each voxel according to its respective distortion factor. Next, a shrinkage of the grid of voxels is simulated according to a sintering process. A negative compensation is applied to the voxel grid, according to the simulated shrinkage of the grid of voxels, to form a compensated voxel grid. Lastly, the change in the voxel grid is mapped to the compensated voxel grid onto the part mesh to create a pre-processed compensated part mesh.