G06F2119/22

Methods for simulating welding processes that can use filler material
11669655 · 2023-06-06 · ·

In one embodiment, a wizard can automate a setup of a welding simulation by requiring the input of data (e.g. in data entry fields labelled as required) that is used to automatically set up a welding simulation. The wizard can be part of a general purpose mechanical simulation software package, and the wizard can receive inputs from CAD software that specifies the geometrical shapes of bodies of the assembly to be welded and the filling material itself and physical properties of bodies to be welded (e.g. sizes of bodies, number of bodies, physical arrangement and geometries of bodies, melting temperatures, etc.), in addition to the material physical properties and the wizard can provide outputs to the mechanical simulation software package to provide boundary conditions for use in the mechanical simulation software that can use finite element analysis methods in simulations.

AUTO COMPACTION TOOL FOR ELECTRONIC DESIGN AUTOMATION
20230169247 · 2023-06-01 ·

A method for manufacturing-aware editing of circuit layouts driven by predictions regarding predicted manufactured wafer contours generated by a machine-trained network. The method allows for fast edit loops in interactive editing timeframes, in which the predicted manufactured wafer contours corresponding to design edits are presented within seconds of the edits themselves. In some embodiments, the wafer contours take mask OPC/ILT and lithography effects into account, as determined by the machine trained network.

PROGRAMMABLE CHIP, DESIGN METHOD AND DEVICE
20210406437 · 2021-12-30 ·

A programmable operation and control chip, comprising: at least one controller with a control flow operation mode; at least one bus; at least one programmable operation structure with data stream flow operation mode which communicates with the controller via the bus and the data buffering structure to control and schedule the programmable operation structure and/or the data buffering structure, and allocate and process serial and parallel operation of data and/or dynamically reconfigure internal structure of the chip.

Mitigating timing yield loss due to high-sigma rare-event process variation
11210448 · 2021-12-28 · ·

Embodiments provide for mitigating parametric yield loss of an integrated circuit (IC) design. In certain embodiments, a delay distribution associated with at least one cell disposed in the design is determined. A pin slack distribution associated with paths in which the at least one cell is disposed is determined. A residual distribution is determined based at least in part on the delay distribution and the pin slack distribution. Yield loss associated with the at least one cell is determined based at least in part on the delay distribution and the residual distribution. When it is determined that that the yield loss associated with the at least one cell exceeds a yield loss threshold, the at least one cell may be identified as a candidate for replacement with a replacement cell.

PLANNING DEVICE, PLANNING METHOD, AND PROGRAM
20210398087 · 2021-12-23 ·

A focus identification unit identifies, based on a mathematical model that simulates behavior of a plurality of subsystems constituting a target system, from among the plurality of subsystems, a focus subsystem that causes a large change in an assessment metric of the target system in response to a change in at least one of an operation condition and a maintenance condition. A plan generation unit generates at least one of an operation plan and a maintenance plan such that the assessment metric is optimized with respect to the focus subsystem.

METHOD OF WAFER LAYOUT AND EXPOSURE SYSTEM OF LITHOGRAPHY MACHINE
20210374316 · 2021-12-02 ·

Embodiments of the present application relate to the technical field of semiconductor, and disclose a design method of a wafer layout and an exposure system of a lithography machine. The design method of a wafer layout includes: providing a yield distribution map of a wafer under an initial wafer layout; determining a yield edge position of the wafer according to the yield distribution map; and calculating a new wafer layout according to a die size and the yield edge position.

WAFER DEFECT PREDICTION DEVICE AND OPERATING METHOD THEREOF
20220207216 · 2022-06-30 · ·

A method of predicting wafer defect information includes estimating a distribution with respect to defect occurrence time data, the defect occurrence time data including information about a time associated with a wafer defect occurrence, distinguishing a defect distribution type according to a result of the estimating the distribution, and outputting wafer defect information predicted according to the distinguished defect distribution type.

VARIABLE SYSTEM FOR SIMULATING OPERATION OF AUTONOMOUS VEHICLES
20220207208 · 2022-06-30 ·

Embodiments of a variable system for simulating the operation of an autonomous system, such as an autonomous vehicle, are disclosed. A layered approach for defining variables can allow changing the specification of those variables under the rules of override and refinement, while leaving the software components that query those variables at runtime unaffected. The variable system can facilitate, among others, deterministic sampling of variables, simulation variations, noise injection, and realistic message timing. These applications can make the simulator more expressive and more powerful by virtue of being able to test the same scenario under many different conditions. As a result, more exhaustive testing can be performed without requiring user intervention and without having to change the individual software components of the simulator.

DEVICE, METHOD AND COMPUTER PROGRAM PRODUCT FOR CHECKING STABILITY
20220198093 · 2022-06-23 ·

The present disclosure relates to a method for checking connection stability of a plurality of assembling elements disposed in a virtual space, each of the assembling elements having at least one coupling part complementarily coupled to another coupling part and being connected to another assembling element through the coupling part. A connection stability checking method includes: assigning preset weight information to the assembling element; calculating a coupling power of the coupling part in consideration of a coupling type and a coupling number of the coupling part; and determining connection stability between the assembling element and another assembling element on the basis of the coupling power and the weight information assigned to the assembling element.

NETWORK CONSTRUCTION SUPPORT SYSTEM
20220198094 · 2022-06-23 · ·

A network construction support system (100) generates one or more pieces of layout data (101) indicating a layout of construction assisting tools (140). The network construction support system calculates a countermeasure cost and an estimated risk amount, for each layout data, the countermeasure cost increasing as a number of units of construction assisting tools increases, the estimated risk amount decreasing as the number of units of construction assisting tools increases and as a narrowed range by each construction assisting tool narrows. The network construction support system judges an appropriateness of the layout data for the apparatus network system, for each layout data, on the basis of a countermeasure cost, an estimated risk amount, and an allowable risk amount which is allowed for the apparatus network system, The network construction support system outputs layout data judged to be appropriate for the apparatus network system.