An embodiment for operation of an emulated electrically erasable (EEE) memory system includes a memory controller configured to identify a first quick record of a stack of quick records as a present record, wherein the stack of quick records are stored in a non-volatile portion of memory, the first quick record has a quick record status identifier (ID) that indicates the stack of quick records has not been qualified, determine a record status of a next record after the present record in the non-volatile portion of memory, and in response to a determination that the next record has a blank record status ID: update the next record from the blank record status ID to the quick record status ID, wherein the blank record status ID indicates that the next record is part of the stack of quick records, and qualify the present record using the plurality of program steps.

According to an example, a dual-port non-volatile dual in-line memory module (NVDIMM) includes a first port to provide a central processing unit (CPU) with access to universal memory of the dual-port NVDIMM and a second port to provide an external NVDIMM manager circuit with access to the universal memory of the dual-port NVDIMM. Accordingly, a media controller of the dual-port NVDIMM may store data received from the CPU through the first port in the universal memory, control dual-port settings received from the CPU, and transmit the stored data to the NVDIMM manager circuit through the second port of the dual-port NVDIMM.

Described are methods, systems and computer readable media for performance logging of complex query operations.

A computer system supports measuring execution time of concurrent threads. A thread allocates a timing buffer in thread local storage. During execution, the thread also has access to a system timer which it can sample with microsecond or better precision with a single instruction. For any sequence of instructions within the thread for which execution time is to be measured, the sequence of instructions has an identifier and includes two commands, herein called a start command and an end command. The start command samples the system timer to obtain a start time, and stores the identifier and the start time in the timing buffer in the thread local storage. The end command samples the system timer to obtain an end time, and updates the data for the corresponding identifier in the timing buffer, to indicate an elapsed time for execution of the sequence of instructions. The start command and end command each can be implemented as a single executable instruction.

As disclosed herein a computer system for secure database backup and recovery in a secure database network has N distributed data nodes. The computer system includes program instructions that include instructions to receive a database backup file, fragment the file using a fragment engine, and associate each fragment with one node, where the fragment is not stored on the associated node. The program instructions further include instructions to encrypt each fragment using a first encryption key, and store, randomly, encrypted fragments on the distributed data nodes. The program instructions further include instructions to retrieve the encrypted fragments, decrypt the encrypted fragments using the first encryption key, re-encrypt the decrypted fragments using a different encryption key, and store, randomly, the re-encrypted fragments on the distributed data nodes. A computer program product and method corresponding to the above computer system are also disclosed herein.

Described are methods, systems and computer readable media for data source refreshing.

An apparatus is disclosed in which the apparatus may include a plurality of cores, including a first core, a second core and a third core, and circuitry coupled to the first core. The first core may be configured to process a plurality of instructions. The circuitry may be may be configured to detect that the first core stopped committing a subset of the plurality of instructions, and to send an indication to the second core that the first core stopped committing the subset. The second core may be configured to disable the first core from further processing instructions of the subset responsive to receiving the indication, and to copy data from the first core to a third core responsive to disabling the first core. The third core may be configured to resume processing the subset dependent upon the data.

The present invention relates to a data storage and retrieval system. The system includes a at least one client device; and at least one-server. The server includes at least one memory, a processor and a log store. The client data is divided into different blocks and stored in the server. Different logs are generated for each block and stored in the log store. The storage in the server are audited for ensuring their integrity. The present invention also relates to a method used to store and retrieve data form the above system. The present invention also relates to a method used to initialize empty buffers in a storage of a system.

A method includes saving a control state for a processor in response to commencing a transactional processing sequence, wherein saving the control state produces a saved control state. The method also includes permitting updates to the control state for the processor while executing the transactional processing sequence. Examples of updates to the control state include key mask changes, primary region table origin changes, primary segment table origin changes, CPU tracing mode changes, and interrupt mode changes. The method also includes restoring the control state for the processor to the saved control state in response to encountering a transactional error during the transactional processing sequence. In some embodiments, saving the control state comprises saving the current control state to memory corresponding to internal registers for an unused thread or another level of virtualization. A corresponding computer system and computer program product are also disclosed herein.

A memory system includes dynamic random-access memory (DRAM) components that include interconnected and redundant component data interfaces. The redundant interfaces facilitate memory interconnect topologies that accommodate considerably more DRAM components per memory channel than do traditional memory systems, and thus offer considerably more memory capacity per channel, without concomitant reductions in signaling speeds. The memory components can be configured to route data around defective data connections to maintain full capacity and continue to support memory transactions.